Third Revision — Includes blitter chip information .

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INTERNALS

The authoritative insider’s guide

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A Data Becker book published by

— ■ You Can Count On yf ^

Abacus Imiii Software

INTERNALS

The authoritative insider’s guide

By K. Gerits, L. Englisch, R. Bruckmann

A Data Becker Book Published by

Abacus mana Software

Third Edition, January 1988 Printed in U.S.A.

5370 52nd Street, S.E.

Grand Rapids, MI 49508

This book is copyrighted. No part of this book may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise without the prior written permission of Abacus Software or Data Becker, GmbH.

Every effort has been made to ensure complete and accurate information concerning the material presented in this book. However, Abacus Software can neither guarantee nor be held legally responsible for any mistakes in printing or faulty instructions contained in this book. The authors will always appreciate receiving notice of subsequent mistakes.

ATARI, 520ST, ST, TOS, ST BASIC and ST LOGO are trademarks or registered trademarks of Atari Corp.

GEM, GEM Draw and GEM Write are trademarks or registered trademarks of Digital Research Inc.

IBM is a registered trademark of International Business Machines.

ISBN

0-916439-46-1

Table of Contents

1	The Integrated Circuits	1
1.1	The 68000 Processor	3
1.1.1	The 68000 Registers	4
1.1.2	Exceptions on the 68000	7
1.1.3	The 68000 Connections	7
1.2	The Custom Chips	13
1.3	The WD 1772 Floppy Disk Controller	20
1.3.1	1772 Pins	20
1.3.2	1772 Registers	24
1.3.3	Programming the FDC	25
1.4	The MFP 68901	28
1.4.1	68901 Connections	28
1.4.2	The MFP Registers	32
1.5	The 6850 ACIAs	41
1.5.1	The Pins of the 6850	41
1.5.2	The Registers of the 6850	44
1.6	The YM-2149 Sound Generator	48
1.6.1	Sound Chip Pins	50
1.6.2	The 2149 Registers and their Functions	52
1.7	I/O Register Layout of the ST	55
2	The Interfaces	65
2.1	The Keyboard	67
2.1.1	The Mouse	71
2.1.2	Keyboard commands	74
2.2	The Video Connection	85
2.3	The Centronics Interface	88
2.4	The RS-232 Interface	90
2.5	The MIDI Connections	93
2.6	The Cartridge Slot	96
2.6.1	ROM Cartridges	97
2.7	The Floppy Disk Interface	99
2.8	The DMA Interface	101
3	The ST Operating System	103
3.1	The GEMDOS	106
3.1.1	Memory, files and processes	145
3.2	The BIOS Functions	152
3.3	The XBIOS	164

i

3.4	The Graphics	206
3.4.1	An overview of the line-A variables	227
3.4.2	Examples for using the line-A opcodes	230
3.5	The Exception Vectors	235
3.5.1	The line-F emulator	238
3.5.2	The interrupt structure of theST	240
3.6	The ST VT52 Emulator	245
3.7	The ST System Variables	250
3.8	The 68000 Instruction Set	258
3.8.1	Addressing modes	259
3.8.2	The instructions	263
3.9	The BIOS Listing	271
4	Appendix	463
4.1	The System Fonts	465
4.2	Alphabetical listing of GEMDOS functions	467
4.3	The blitter chip	469
4.3.1	The blitter registers	471
4.4	The Mega ST realtime clock	478
4.5	Blitter chip demonstration programs	479
	Index	491

II

List of Figures

1.1-1	68000 Registers	5
1.2-1	GLUE	14
1.2-2	MMU	16
1.2-3	SHIFTER	17
1.2-4	DMA	19
1.3-1	FDC 1772	21
1.4-1	MFP 68901	29
1.5-1	ACIA 6850	42
1.6-1	Sound Chip YM-2149	49
1.6-2	Envelopes of the PSG	53
1.7-1	I/O Assignments	62
1.7-2	Memory Map	63
1.7-3	Block Diagram of the Atari ST	64
2.1-1	6850 Interface to 68000	68
2.1-2	Block Diagram of Keyboard Circuit	70
2.1. 1-1	The Mouse	72
2.1. 1-2	Mouse control port	74
2.1.2-1	Atari ST Key Assignments	84
2.2-1	Diagram of Video Interface	86
2.2-2	Monitor Connector	87
2.3-1	Printer Port Pins	88
2.3-2	Centronics Connection	89
2.4-1	RS-232 Connection	92
2.5-1	MIDI System Connection	95
2.6-1	The Cartridge Slot	96
2.7-1	Disk Connection	100
2.8-1	DMA Port	102
2.8-2	DMA Connections	102
3.4-1	Lo-Res-Mode	208
3.4-2	Medium-Res-Mode	209
3.4-3	Hi-Res-Mode	210
4.3-1	BLITTER	469
4.3.1-1	BLITTER BLOCK DIAGRAM	471

m

Chapter One

- .

The Integrated Circuits _ /

1.1 The 68000 Processor

1.1.1 The 68000 Registers

1.1.2 Exceptions on the 68000

1.1.3 The 68000 Connections

1.2 The Custom Chips

1.3 The WD 1772 Floppy Disk Controller

1.3.1 1772 Pins

1.3.2 1772 Registers

1.3.3 Programming the FDC

1.4 The MFP 68901

1.4.1 68901 Connections

1.4.2 The MFP Registers

1.5 The 6850 ACIAs

1.5.1 The Pins of the 6850

1.5.2 The Registers of the 6850

1.6 The YM-2149 Sound Generator

1.6.1 Sound Chip Pins

1.6.2 The 2149 Registers and their Functions

1.7 I/O Register Layout of the ST

Abacus Software

Atari ST Internals

The Integrated Circuits

1.1 The 68000 Processor

The 68000 microprocessor is the heart of the entire Atari ST system. This 16-bit chip is in a class by itself; programmers and hardware designers alike find the chip very easy to handle. From its initial development by Motorola in 1977 to its appearance on the market in 1979, the chip was to be a competitor to the INTEL 8086/8088 (the processor used in the IBM-PC and its many clones). Before the Atari ST's arrival on the marketplace, there were no affordable 68000 machines available to the home user. Now, though, with 16-bit computers becoming more affordable to the common man, the 8-bit machines won't be around much longer.

What does the 68000 have that's so special? Here’s a very incomplete list of features:

16 data bits

24 address bits (16- megabyte address range!!) all signals directly accessible without multiplexer hassle-free operation of "old" 8-bit peripherals powerful machine language commands easy-to-leam assembler syntax 14 different types of addressing

17 registers each having 32-bit widths

These specifications (and many yet to be mentioned here) make the 68000 an incredibly good microprocessor for home and personal computers. In fact, as the price of memory drops, you'll soon be seeing 68000-based 64K machines for the same price as present-day 8-bit computers with the same amount of memory.

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1.1.1 The 68000 Registers

Let's take a look at 68000 design. Figure 1.1-1 shows the 17 onboard 32-bit registers, the program counter and the status register.

The eight data registers can store and perform calculations, as well as the normal addressing tasks. Eight-bit systems use the accumulators for this, which limits the programmer to a total of 8 accumulators. Our 68000 data registers are quite flexible; data can be handled in 1-, 8-, 16- and 32- bit sizes. Even four-bit operations are possible (within the limits of Binary Coded Decimal counting). When working with 32-bit data, all 32 bits can be handled with a single operation. With 8- and 16-bit data, only the 8th or 16th bit of the data register can be accessed.

The address registers aren't as flexible for data access as are the data registers. These registers are for addressing, not calculation. Processing data is possible only with word (16-bit) and longword (32-bit) operations. The address registers must be looked at as two distinct groups, the most versatile being the registers A0-A6. Registers A7 and A7' fulfill a special need. These registers are used as the stack pointer by the processor. Two stack pointers are needed to allow the 68000 to run in USER MODE and SUPERVISOR MODE. Register A7 declares whether the system is in USER or SUPERVISOR mode. Note that the two registers work "under" A7, but the register contents are only available to the respective operating mode. We'll discuss these operating modes later.

The program counter is also considered a 32-bit register. It is theoretically possible to handle an address range of over 4 gigabytes. But the address bits A24-A31 aren't used, which "limits" us to 16 megabytes.

The 68000 status register comprises 16 bits, of which only 10 bits are used. This status register is divided into two halves: The lower eight bits (bits 0 to 4 proper) is the "user byte". These bits, which act as flags most of the time, show the results of arithmetical and comparative operations, and can be used for program branches hinging on those results. We'll look at the user byte in more detail later; for now, here is a brief list:

BIT 0 = Carry flag BIT 1 = Overflow flag

BIT 2 = Zero flag BIT 3 = Negative flag

BIT 4 = extend flag

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Abacus Software

Atari ST Internals

Abacus Software

Atari ST Internals

Bits 8-10, 13 and 15 make up the status register's system byte. The remaining bits are unused. Bit 15 works as a trace bit, which lets you do a software controlled single-step execution of any program. Bit 13 is the supervisor bit. When this bit is set, the 68000 is in supervisor mode. This is the normal operating mode; all commands are executed in this mode. In user mode, in which programs normally run, privileged instructions are inoperative. A special hardware design allows access into the other memory range while in user mode (e.g., important system variables, I/O registers). The system byte of the status register can only be manipulated in supervisor mode; but there's a simple method of switching between modes.

Bits 8 and 10 show the interrupt mask, and run in connection with pins IPL0-IPL2.

The 68000 has great potential for handling interrupts. Seven different interrupt priorities exist, the highest being the "non-maskable interrupt"; NMI. This interrupt recognizes when all three IPL pins simultaneously read low (0). If, however, all three IPL pins read high, there is no interrupt, and the system operates normally. The other six priorities can be masked by appropriate setting of the system byte of the status register. For example, if bit 12 of the interrupt mask is set, while 10 and II are off, only levels 7, 6 and 5 (000, 001 and 010) are recognized. All other combinations from IPL0-IPL2 are ignored by the processor.

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Abacus Software

Atari ST Internals

1.1.2 Exceptions on the 68000

We've spoken of interrupts as if the 68000 behaves like other microprocessors. Interrupts, according to Motorola nomenclature, are an external form of an exception (the machine can interrupt what it's doing, do something else, and return to the interrupted task if needed). The 68000 distinguishes between normal operation and exception handling, rather than between user and supervisor mode. One such set of exceptions are the interrupts. Other things which cause exceptions are undefined opcodes, and word or longword access to a prohibited address.

To make exception handling quicker and easier, the 68000 reserves the first IK of memory (1024 bytes, $000000-$0003FF). The exception table is located here. Exceptions are all coded as one of four bytes of a longword. Encountering an exception triggers the 68000, and the address of the corresponding table entry is output

A special exception occurs on reset, which requires 8 bytes (two longwords); the first longword contains the standard initial value of the supervisor stack pointer, while the second longword contains the address of the reset routine itself. See Chapter 3.3 for the design and layout of the exception table.

1.1.3 The 68000 Connections

The connections on the 68000 are divided into eight groups (see Figure 1.1-3 on page 11).

The first group combines data and address busses. The data bus consists of pins D0-D15, and the address bus A1-A23. Address bit A0 is not available to the 68000. Memory can be communicated with words rather than bytes (1 word=2 bytes=16 bits, as opposed to 1 byte=8 bits). Also, the 68000 can access data located on odd addresses as well as even addresses. The signals will be dealt with later.

It's important to remember in connection with this, that by word access to memory, the byte of the odd address is treated as the low byte, and the even

7

Abacus Software

Atari ST Internals

address is the high byte. Word access shouldn't stray from even addresses. That means that opcodes (whether all words or a single word) must always be located at even addresses.

When the data and address bus are in "tri-state” condition, a third condition (in addition to high and low) exists, in which the pins offer high resistance, and thus are inactive on the bus. This is important in connection with Direct Memory Access (DMA).

The second group of connections comprise the signals for asynchronous bus control. This group has five signals, which we’ll now look at individually:

1) R/W (READ/WRITE)

The R/W signal is a familiar one to all microprocessors. This indicates to memory and peripherals whether the processor is writing to or reading data from the address on the bus.

2) AS (ADDRESS STROBE)

Every processor has a signal which it sends along the data lines signaling whether the address is ready to be used. On the 68000, this is known as the ADDRESS STROBE (low active).

3) UDS (UPPER DATA STROBE)

4) LDS (LOWER DATA STROBE)

If the 68000 could only process an entire memory word (two bytes) simultaneously, this signal wouldn't be necessary. However, for individual access to the low-byte and high-byte of a word, the processor must be able to distinguish between the two bytes. This is the task performed by UDS and LDS. When a word is accessed, both strobes are activated simultaneously (active=low). Accessing the data at an odd address activates the Lower Data Strobe only, while accessing data at an even address activates the Upper Data Strobe.

Bit A0 from the address bus is used in this case. After every access when the system must distinguish between three conditions (word, even byte, odd byte), A0 determines how to complete the access.

LDS and UDS are tri-state outputs.

8

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Atari ST Internals

5) DTACK

The above signals (with the exception of UDS and LDS) are needed by an 8-bit processor. DTACK takes a different path; DTACK must be low for any write or read access to take place. If the signal is not low within a bus cycle, the address and data lines "freeze up" until DTACK turns low. This can also occur in a WAIT loop. This way, the processor can slow down memory and peripheral chips while performing other tasks. If no wait cycles are used on the ST, the processor moves "at full tilt".

The third group of connections, the signals VMA, VPA and E are for synchronous bus control. A computer is more than memory and a microprocessor; interfaces to keyboard, screen, printer, etc. must be available for communication. In most cases, interfacing is handled by special ICs, but the 68000 has a huge selection of interface chips onboard. For hardware designers we'll take a little time explaining these synchronous bus signals.

The signal E (also known as 02 or phi 2) represents the reference count for peripherals. Users of 6800 and 6502 machines know this signal as the system counter. Whereas most peripheral chips have a maximum frequency of only 1 or 2 mHz, the 68000 has a working speed of 8 mHz, which can increased to 10 by the E signal. The frequency of E in the ST is 800 kHz. The E output is always active; it is not capable of a TRI- STATE condition.

The signal VPA (Valid Peripheral Address) sends data over the synchronous bus, and delegates this transfer to specific sections of the chip. Without this signal, data transfer is performed by the asynchronous bus. VPA also plays a role in generating interrupts, as we'll soon see.

VMA (Valid Memory Address) works in conjunction with the VPA to produce the CHIP-select signal for the synchronous bus.

The fourth group of 68000 signals allows simple DMA operation in the 68000 system. DMA (Direct Memory Access) directly accesses the DMA controllers, which control computer memory, and which is the fastest method of data transfer within a computer system.

To execute the DMA, the processor must be in an inactive state. But for the processor to be signaled, it must be in a "sleep" state; the low BR signal

9

Abacus Software

Atari ST Internals

(Bus Request) accomplishes this. On recognizing the BR signal, the 68000’s read/write cycle ends, and the BG signal (Bus Grant) is activated. Now the DMA-requested chip waits until the signals AS, DTACK and (when possible) BGACK are rendered inactive. As soon as this occurs, the BGACK (Bus Grant Acknowledge) is activated by the requested chip , and takes over the bus. All essential signals on the processor are made high; in particular, the data, address and control busses are no longer influenced by the processor. The DMA controller can then place the desired address on the bus, and read or write data. When the DMA chip is finished with its task, the BGACK signal returns to its inactive state, and the processor again takes over the bus.

The fifth group of signals on the 68000 control interrupt generation. The 68000's "user's choice" interrupt concept is one of its most extraordinary performing qualities; you have 199 (!) interrupt vectors from which to choose. These interrupt vectors are divided into 7 non- auto- vectors and 192 auto-vectors, plus 7 different priority lines.

Interrupts are triggered by signals from the three lines IPLO to IPL2; these three lines give you eight possible combinations. The combination determines the priority of the interrupt. That is, if IPLO, IPL1 and IPL2 are all set high, then the lowest priority is set ("no interrupt"). However, if all three lines are low, then highest priority takes over, to execute a non-maskable interrupt. All the combinations in between affect special bits in the 68000's status register; these, in turn, affect program control, regardless of whether or not a chosen interrupt is allowable.

Wait - what are auto- vectors and non-auto- vectors? What do these terms mean?

If requesting an interrupt on IPL0-IPL2 while VPA is active (low), the desired code is directly converted from the IPL pins into a vector number. All seven interrupt codes on the IPL pins have their own vectors, though. The auto- vector concept automatically gives the vector number of the IPL interrupt code needed.

When DTACK, instead of VPA, is active on an interrupt request, the interrupt is handled as a non-auto-vector. In this case, the vector number from the triggered chip is produced by DTACK on the 8 lowest bits of the data bus. Usually (though not important here), the vector number is placed into the user- vector range ($40~$FF).

10

Abacus Software

Atari ST Internals

The sixth set of connections are the three "function code" outputs FCO to FC2. These lines handle the status display of the processor. With the help of these lines, the 68000 can expand to four times 16 megabytes (64 megabytes). This extension requires the MMU (Memory Management Unit). This MMU does more than handle memory expansion on the ST; it also recognizes whether access is made to memory in user or supervisor mode. This information is conveyed to a memory range only accessible in supervisor mode. Also, the interrupt verification uses this information on the FC line. The figure below shows the possible combinations of functions.

Figure 1.1-3

E£2 E £1 _ ECU

0 0 0

0 0 1

0 10 Oil 10 0 10 1 110 111

Status

unused

User-mode data access User-mode program unused unused

Supervisor data access Supervisor program Interrupt verification

The seventh group contains system control signals. This group applies to the input CLK and BERR, as well as the bidirectional lines RESET and HALT.

The input CLK will generate the working frequency of the processor. The 68000 can operate at different speeds; but the operating frequency must be specified (4, 6, 8, 10, or even 12.5 mHz). The ST has 8 mHz built in, while the minimum operating frequency is 2 mHz. The ST's 8 mHz was chosen as a "middle of the road" frequency to avoid losing data at higher frequencies.

The RESET line is necessary to check for system power-up. The 68000's uata page distinguishes between two different reset conditions. On power-up, RESET and HALT are switched low for at least 100 milliseconds, to set up a proper initialization. Every other initialization requires a low impulse of at least 4 "beats" on the 68K.

Here is what RESET does in detail. The system byte of the status register is loaded with the value $27. Once the processor is brought into supervisor

11

Abacus Software

Atari ST Internals

status, the Trace flag in the status register is cleared, and the interrupt level is set to 7 (lowest priority, all lines allowable). Additionally, the supervisor stack pointer and program counter are loaded with the contents of the first 8 bytes of memory, whereby the value of the program counter is set to the beginning of the reset routine.

However, since the RESET line is bi-directional, the processor can also have RESET under program control during the time the line is low. The RESET instruction serves this pupose, when the connection is low for 124 beats". It's possible to re-initialize the peripheral ICs at any time, without resetting the computer itself. RESET time puts the 68000 into a NOP state - a reset is unstoppable once it occurs.

The HALT pin is important to the RESET line's existence (as we mentioned above), in order to initialize things properly. This pin has still more functions: when the pin is low while RESET is high, the processor goes into a halt state. This state causes the DMA pin to set the processor into the tri-state condition. The HALT condition ends when HALT is high again. This signal can be used in the design of single-step control.

HALT is also bi-directional. When the processor signals this line to become low, it means that a major error has occurred (e.g., doubled bus and address errors).

A low state on the BERR pin will call up exception handling, which runs basically like an external interrupt. In an orderly system, every access to the asynchronous bus quits with the DTACK signal. When DTACK is outputting, however, the hardware can produce a BERR, which informs the processor of any errors found. A further use for BERR is in connection with the MMU, to test for proper memory access of a specific range; this access is signaled by the FC pins. If protected memory is tried for in user mode, a BERR will turn up.

When both BERR and HALT are low, the processor will "re-execute" the instruction at which it stopped. If it doesn't run properly on the second "go-round", then it's called a doubled bus error, and the processor halts.

The eighth group of connections are for voltage and ground.

12

Abacus Software

Atari ST Internals

1.2 The Custom Chips

The Atari ST has four specially developed ICs. These chips (GLUE, MMU, DMA and SHIFTER) play a major role in the low price of the ST, since each chip performs several hundred overlapping functions. The first prototype of the ST was 5 X 50 X 30 cm. in size, mostly to handle all those TTL ICs. Once multiple functions could be crammed into four ICs, the ST became a saleable item. Then again, the present ST hasn't quite reached the ultimate goal — it still has eight TTLs.

Naturally, since these chips were specifically designed by Atari for the ST, they haven't been publishing any spec sheets. Even without any data specs, we can give you quite a bit of information on the workings of the ICs.

An interesting fact about these ICs is that they're designed to work in concert with one another. For example, the DMA chip can't operate alone. It hasn't an address counter, and is incapable of addressing memory on its own (functions which are taken care of by the MMU). It's the same with SHIFTER - it controls video screen and color, but it can't address video RAM. Again, MMU handles the addressing.

The system programmer can easily figure out which IC has which register. It is only essential to be able to recognize the address of the register, and how to control it. We’re going to spend some time in this chapter exploring the pins of the individual ICs.

The most important IC of the "foursome" is GLUE. Its title speaks for the function - a glue or paste. This IC, with its 68 pins, literally holds the entire system together, including decoding the address range and working the peripheral ICs.

Furthermore, the DMA handshake signals BR, BG and BGACK are produced/output by GLUE. The time point for DMA request is dictated by GLUE by the signal from the DMA controller. GLUE also has a BG (Bus Grant) input, as well as a BGO (Bus Grant Out).

The interrupt signal is produced by GLUE; in the ST, only IPL1 and IPL2 are used for this. Without other hardware, you can't use NMI (interrupt level 7). The pins MFPINT and IACK are used for interrupt control.

13

Abacus Software

Atari ST Internals

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14

Abacus Software

Atari ST Internals

The function code pins are guided by GLUE, where memory access tasks are performed (range testing and access authorization). Needless to say, the BERR signal is also handled by this chip. VPA is particularly important to the peripheral ICs and the appropriate select signals.

GLUE generates a timing frequency of 8 mHz. Frequencies between 2 mHz (sound chip's operating frequency) and 500 kHz (timing for keyboard and MIDI interface) can be produced.

HSYNC, VSYNC, BLANK and DE (Display Enable) are generated by GLUE for monitor operation. The synchronous timing can be switched on and off, and external sync-signals sent to the monitor. This will allow you to synchronize the ST's screen with a video camera.

The MMU also has a total of 68 pins. This IC performs three vital tasks. The most important task is coupling the multiplexed address bus of dynamic RAM with the processor's bus (handled by address lines A1 to A21). This gives us an address range totaling 4 megabytes. Dynamic RAM is controlled by RASO, RAS1, CASOL, CASOH, CAS1L and CAS1H, as well as the multiplexed address bus on the MMU. DTACK, R/W, AS, LDS and UDS are also controlled by MMU.

We've already mentioned another important function of the MMU: it works with the SHIFTER to produce the video signal (the screen information is addressed in RAM, and SHIFTER conveys the information). Counters are incorporated in the MMU for this; a starting value is loaded, and within 500 nanoseconds, a word is addressed in memory and the information is sent over DCYC. The starting value of the video counter (and the screen memory position) can be shifted in 25 6- byte increments.

Another integrated counter in MMU, as mentioned earlier, is for addressing memory using the DMA. This counter begins with every DMA access (disk or hard disk), loading the address of the data being transferred. Every transfer automatically increments the counter.

The SHIFTER converts the information in video RAM into impulses readable on a monitor. Whether the ST is in 640 X 200 or 320 X 200 resolution, SHIFTER is involved.

15

Abacus Software

Atari ST Internals

Figure 1.2-2 MMU

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16

Abacus Software

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The information from RAM is transferred to SHIFTER on the signal LOAD. A resolution of 640 X 400 points sends the video signal over the MONO connector. Since color is impossible in that mode, the RGB connection is rendered inactive. The other two resolutions set MONO output to inactive, since all screen information is being sent out the RGB connection in those cases.

The third color connection works together with external equipment as a digital/analog converter. Individual colors are sent out over different pins, to give us color on our monitor. Pins Rl- R5 on the address bus make up the "palette registers". These registers contain the color values, which are placed in individual bit patterns. The 16 palette registers hold a total of 16 colors for 320 X 200 mode. Note, however, that since these are based on the "primary" colors red, green and blue, these colors can be adjusted in 8 steps of brightness, bringing the color total to 5 12.

The DMA controller is like SHIFTER, only in a 40-pin housing; it is used to oversee the floppy disk controller, the hard disk, and any other peripherals that are likely to appear.

The speed of data transfer using the floppy disk drive offers no problems to the processor. It's different with hard disks; data moves at such high speed that the 68000 has to send a "pause" over the 8 mHz frequency. This pace is made possible by the DMA.

The DMA is joined to the processor's data bus to help transfer data. Two registers within the machine act as a bi-directional buffer for data through the DMA port; we’ll discuss these registers later. One interesting point: The processor's 16-bit data bus is reduced to 8 bits for floppy/hard disk work. Data transfer automatically transfers two bytes per word.

The signals CA1, CA2, CRAY, FDCS and FDRQ manage the floppy disk controller. CA1 and CA2 are signals which the floppy disk controller (FDC) uses to select registers. CR/W determine the direction of data transfer from/to the FDC, and other peripherals connected to the DMA port.

The RDY signal communicated with GLUE (DMA-request) and MMU (address counter). This signal tells the DMA to transfer a word.

As you can see, these ICs work in close harmony with one another, and each would be almost useless on its own.

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Figure 1.2-4 DMA

V c c CLK R D Y ACK*

C D 0 C D 1 CD 2 CD 3 CD 4 CD 5 CD 6 CD 7 G N D C A 2 C A 1 CR/W* HDCS * HD RQ FD C S * FDRQ

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1.3 The WD 1772 Floppy Disk Controller

Although the 1772 from Western Digital has only 28 pins, this chip contains a complete floppy disk controller (FDC) with capabilities matching 40-pin controllers. This IC is software-compatible with the 1790/2790 series. Here are some of the 1772's features:

Simple 5-volt current Built-in data separator Built-in copy compensation logic Single and double density Built-in motor controls

Although the user has his/her choice of disk format, e.g. sector length, number of sectors per track and number of tracks per diskette, the "normal" format is the optimum one for data transfer. So, Apple or Commodore diskettes can't be used.

Before going on to details of the FDC, let's take a moment to look at the 28 pins of this IC.

1.3.1 1772 Pins

These pins can be placed in three categories. The first group consists of the power connections.

Vcc:

+5 volts current.

GND:

Ground connection.

MR:

Master reset. FDC reinitializes when this is low.

The second set are processor interface pins. These pins carry data between the processor and the FDC.

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Figure 1.3-1 FDC 1772

INTR DRQ D D * HP* INDEX TRK 0 W D W G M 0 RD *

C LK D I RC STEP Vcc

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D0-D7:

Eight-bit bi-directional bus; data, commands and status information go between FDC and system.

CS:

FDC can only access registers when this line is low.

R/W:

Read/Write. This pin states data direction. HIGH= read by FDC, LOW= write from FDC.

A0,A1:

These bits determine which register is accessed (in conjunction with R/W). The 1772 has a total of five registers which can both read and write to some degree. Other registers can only read OR write. Here is a table to show how the manufacturer designed them:

A1

0

1

A Q _ R/W=l

0 Status Reg.

1 Track Reg.

0 Sector Reg.

1 Data Reg.

R/W=0

Command Reg . Track Reg. Sector Reg. Data Reg.

DRQ:

Data Request. When this output is high, either the data register is full (from reading), and must be "dumped", or the data register is empty (writing), and can be refilled. This connection aids the DMA operation of the FDC.

CLK:

Clock. The clock signal counts only to the processor bus. An input frequency of 8 mHz must be on, for the FDC's internal timing to work.

The third group of signals make up the floppy interface.

STEP:

Sends an impulse for every step of the head motor.

DIRC:

Direction. This connection decides the direction of the head; high moves the head towards center of the diskette.

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RD:

Read Data. Reads data from the diskette. This information contains both timing and data impulses — it is sent to the internal data separator for division.

MO:

Motor On. Controls the disk drive motor, which is automatically started during read/write/whatever operations.

WG:

Write Gate. WG will be low before writing to diskette. Write logic would be impossible without this line.

WD:

Write Data. Sends serial data flow as data and timing impulses.

TROO:

Track 00. This moves read/write head to track 00. TROO would be low in this case.

IP:

Index Pulse. The index pulses mark the physical beginnings of every track on a diskette. When formatting a disk, the FDC marks the start of each track before formatting the disk.

WPRT:

Write Protect. If the diskette is write-protected, this input will react.

DDEN:

Double Density Enable. This signal is confined to floppy disk control; it allows you to switch between single-density and double-density formats.

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1.3.2 1772 Registers

CR (Command Register):

Commands are written in this 8-bit register. Commands should only be written in CR when no other command is under execution. Although the FDC only understands 11 commands, we actually have a large number of possibilities for these commands (we'll talk about those later).

STR (Status Register):

Gives different conditions of the FDC, coded into individual bits. Command writing depends on the meaning of each bit. The status register can only be read.

TR (Track Register):

Contains the current position of the read/write head. Every movement of the head raises or lowers the value of TR appropriately. Some commands will read the contents of TR, along with information read from the disk. The result affects the Status Register. TR can be read/written.

SR (Sector Register):

SR contains the number of sectors desired from read/write operations. Like TR, it can be used for either operation.

DR (Data Register):

DR is used for writing data to/ reading data from diskette.

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1.3.3 Programming the FDC

Programming this chip is no big deal for a system programmer. Direct (and in most cases, unnecessary) programming is made somewhat harder AND drastically simpler by the DMA chip. The 1 1 FDC commands are divided into four types.

Type Function

1 Restore, look for track 00

1 Seek, look for a track

1 Step, a track in previous direction

1 Step In, move head one track in (toward disk hub)

1 Step Out, move head one track out (toward edge of disk)

2 Read Sector

2 Write Sector

3 Read Address, read ID

3 Read Track, read entire track

3 Write Track, write entire track (format)

4 Force Interrupt

Type 1 Commands

These commands position the read/write head. The bit patterns of these five commands look like this:

BIT

	7	6	5	4	3	2	1	0
Restore	0	0	0	0	H	V	Rl	R0
Seek	0	0	0	1	H	V	Rl	R0
Step	0	0	1	U	H	V	Rl	R0
Step In	0	1	0	u	H	V	Rl	R0
Step Out	0	1	1	u	H	V	Rl	R0

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All five commands have several variable bits; bits RO and R1 give the time between two step impulses. The possible combinations are:

R1 RO STEP RATE

0 02 milliseconds

0 13 milliseconds

1 05 milliseconds

1 16 milliseconds

These bits must be set by the command bytes to the disk drive. The V-bit is the so-called "verify flag". When set, the drive performs an automatic verify after every head movement. The H-bit contains the spin-up sequence. The system delays disk access until the disk motor has reached 300 rpm. If the H-bit is cleared, the FDC checks for activation of the motor-on pins. When the motor is off, this pin will be set high (motor on), and the FDC waits for 6 index impulses before executing the command. If the motor is already running, then there will be no waiting time.

The three different step commands have bit 4 designated a U- bit. Every step and change of the head appears here.

Type 2 Commands

These commands deal with reading and writing sectors. They also have

individual bits with special meanings.
BIT 7 6 5 4 3	2	1	0
Read Sector 1 0 0 M H	E	0	0
Write Sector 1 0 1 M H	E	P	A0

The H-bit is the previously described start-up bit. When the E-bit is set, the FDC waits 30 milliseconds before starting the command. This delay is important for some disk drives, since it takes time for the head to change tracks. When the E-bit reads null, the command will run immediately.

The M-bit determines whether one or several sectors are read one after another. On a null reading, only one sector will be read from/written to. Multi-sector reading sets the bit, and the FDC increments the counter at each new sector read.

Bits 0 and 1 must be cleared for sector reading. Writing has its own special meaning: the A0 bit conveys to bit 0 whether a cleared or normal data

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address mark is to be written. Most operating systems don't use this option (a normal data address mark is written).

The P-bit (bit 1) dictates whether pre-compensation for writing data is turned on or off. Pre-compensation is normally set on; it supplies a higher degree of protection to the inner tracks of a diskette.

Type 3 Commands

Read Address gives program information about the next ED field on the diskette. This ID field describes track, sector, disk side and sector length. Read Track gives all bytes written to a formatted diskette, and the data "between sectors". Write Track formats a track for data storage. Here are the bit patterns for these commands:

BIT

Read Address Read Track Write Track

76543210

1100HE00

1110HE00

1111HEP0

The H- and E-bits also belong to the Type 2 command set (spin-up and head-settle time). The P-bit has the same function as in writing sectors.

Type 4 Commands

There's only one command in this set: Force Interrupt. This command can work with individual bits during another FDC command. When this command comes into play, whatever command was currently running is ended.

BIT 76543210

Force Interrupt 1 1 0 1 13 12 II 10

Bits 10-13 present the conditions under which the interrupt is pressed. 10 and II have no meaning to the 1772, and remain low. If 12 is set, an interrupt will be produced with every index impulse. This allows for software controlled disk rotation. If 13 is set, an interrupt is forced immediately, and the currently-running command ends. When all bits are null, the command ends without interruption.

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1.4 The MFP 68901

MFP is the abbreviation for Multi-Function Peripheral. This name is no exaggeration; wait until you see what it can do! Here's a brief list of the most noteworthy features:

8 -bit parallel port

Data direction of every port bit is individually programmable

Port bits usable as interrupt input

16 possible interrupt sources

Four universal timers

Built-in serial interface

1.4.1 The 68901 Connections

The 48 pins of the MFP are set apart in function groups. The first function group is the power connection set:

GND, Vcc, CLK:

Vcc and GND carry voltage to and from the MFP. CLK is the clock input; this clock signal must not interfere with the system timer of the processor. The ST's MFP operates at a frequency of 4 mHz.

Communication with the data bus of the processor is maintained with D0-D7, DTACK, RS 1-RS5 and RESET.

D0-D7:

These bi-directional pins normally work with the 8 lowest data bits of the 68000. It is also possible to connect with D8 through D15, but it's impossible to produce non-auto interrupts. Thus, interrupt vectors travel along the low order 8 data bits.

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Figure 1.4-1 MFP 68901

c s *

D S *

D TACK * I ACK*

D 7

D 6

D 5

D 4

D 3

D 2

D 1

D 0

V s S C L K X E I *

X E O * INTR*

R R *

T R *

I 7 I 6 I 5 X 4 13

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CS (Chip Select):

This line is necessary to communication with the MFP. CS is active when low.

DS (Data Strobe):

This pin works with either LDS or UDS on the processor. Depending on the signal, MFP will operate either the lower or upper half of the data bus.

DTACK (Data Transfer ACKnoledge):

This signal shows the status of the bus cycle of the processor (read or write).

RS1-RS5 (Register Select):

These pins normally connect with to the bottom five address lines of the processor, and serve to choose from the 24 internal registers.

RESET:

If this pin is low for at least 2 microseconds, the MFP initializes. This occurs on power-up and a system reset.

The next group of signals cover interrupt connections (IRQ, IACK, IEI and IEO).

IRQ (Interrupt ReQuest):

IRQ will be low when an interrupt is triggered in the MFP. This informs the processor of interrupts.

IACK (Interrupt ACKnowledge):

On an interrupt (IRQ and IEI), the MFP sends a low signal over IACK and DS on the data lines. Since 16 different interrupt sources are available, this makes handling interrupts much simpler.

IEI, IEO (Interrupt Enable In/ Out):

These two lines permit daisy-chaining of several MFPs, and determine MFP priority by their positioning in this chain. IEI would work through the MFP with the highest priority. IEO of the second MFP would remain unswitched. On an interrupt, a signal is sent over IACK, and the first MFP in the chain will acknowledge with a high IEO.

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Next, we'll look at the eight I/O lines.

100-7 (Input/Output):

These pins use one or all normal I/O lines. The data direction of each port bit is set up in a data direction register of its own. In addition, though, every port bit can be programmed to be an interrupt input.

The timer pins make up yet another group of connections:

XTAL1,2 (Timer Clock Crystal):

A quartz crystal can be connected to these lines to deliver a working frequency for the four timers.

TAI,TBI (Timer Input):

Timers A and B can not only be used as real counters differently from timers C and D with the frequency from XTAL1 and 2, but can also be set up for event counting and impulse width measurement. In both these cases, an external signal (Timer Input) must be used.

TAO,TBO,TCO,TDO (Timer Output):

Every timer can send out its status on each peg (from 01 to 00). Each impulse is equal to 01.

The second-to-last set of signals are the connections to the universal serial interface. The built-in full duplex of the MFP can be run synchronously or asynchronously, and in different sending and receiving baud rates.

SI (Serial Input):

An incoming bit current will go up the SI input.

SO (Serial Output):

Outgoing bit voltage (reverse of SI).

RC (Receiver Clock):

Transfer speed of incoming data is determined by the frequency of this input; the source of this signal can, for example, be one of the four timers.

TC (Transmitter Clock):

Similar to RC, but for adjusting the baud-rate of data being transmitted.

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The final group of signals aren't used in the Atari ST. They are necessary when the serial interface is operated by the DMA.

RR (Receiver Ready):

This pin gives the status of the receiving data registers. If a character is completely received, this pin sends current.

TR (Transmitter Ready):

This line performs a similar function for the sender section of the serial interface. Low tells the DMA controller that a new character in the MFP must be sent.

1.4.2 The MFP Registers

As we've already mentioned, the 68901 has a total of 24 different registers. This large number, together with the logical arrangement, makes programming the MFP much easier.

Reg 1 GPIP, General Purpose I/O Interrupt Port

This is the data register for the 8-bit ports, where data from the port bits is sent and read.

Reg 2 AER, Active Edge Register

When port bits are used for input, this register dictates whether the interrupt will be a low-high- or high-low conversion. Zero is used in the high-low change, one for low-high.

Reg 3 DDR, Data Direction Register

We've already said that the data direction of individual port bits can be fixed by the user. When a DDR bit equals 0, the corresponding pin becomes an input, and 1 makes it an output. Port bit positions are influenced by AER and DDR bits.

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Reg 4,5 IERA,IERB, Interrupt Enable Register

Every interrupt source of the MFP can be separately switched on and off. With a total of 16 sources, two 8-bit registers are needed to control them. If a 1 has been written to IERA or IERB, the corresponding channel is enabled (turned on). Conversely, a zero disables the channel. If it comes upon a closed channel caused by an interrupt, the MFP will completely ignore it. The following table shows which bit is coordinated with which interrupt occurrence:

IERA Bit 7: Bit 6: Bit 5 : Bit 4: Bit 3: Bit 2: Bit 1: Bit 0:

I/O port bit 7 (highest priority) I/O port bit 6 Timer A

Receive buffer full Receive error Sender buffer empty Sender error Timer B

IERB Bit 7: Bit 6: Bit 5 : Bit 4 : Bit 3: Bit 2 : Bit 1: Bit 0:

I/O	port	bit	5
I/O	port	bit	4
Timer C
Timer D
I/O	port	bit	3
I/O	port	bit	2
I/O	port	bit	1
I/O	port	bit	0,

lowest priority

This arrangement applies to the IP-, IM- and IS-registers discussed below.

Reg 6,7 IPRA,IPRB, Interrupt Pending Register

When an interrupt occurs on an open channel, the appropriate bit in the Interrupt Pending Register is set to 1. When working with a system that allows vector creation, this bit will be cleared when the MFP puts the vector number on the data bus. If this isn't possible, die IPR must be cleared using software. To clear a bit, a byte in the MFP will show the location of the specific bit.

The bit arrangement of the IPR bit arrangement is shown in the table for registers 4 and 5 (see above).

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Reg 8,9 ISRA,ISRB, Interrupt In-Service Register

The function of these registers is somewhat complicated, and depends upon bit 3 of register 12. This bit is an S-bit, which determines whether the 68901 is working in "Software End-of- Interrupt" mode (SEI) or in "Automatic End-of-Interrupt" mode (AEI). AEI mode clears the IPR (Interrupt Pending Bit), when the processor gets the vector number from the MFP during an LACK cycle. The appropriate In-Service bit is cleared at the same time. Now a new interrupt can occur, even when the previous interrupt hasn't finished its work.

SEI mode sets the corresponding ISR-bit when the vector number of the interrupt is requested by the processor. At the interrupt routine's end, the bit designated within the MFP must be cleared. As long as the Interrupt In-Service bit is set, all interrupts of lower priority are masked out by the MFP. Once the Pending-bit of the active channel is cleared, the same sort of interrupt can occur a second time, and interrupts of lesser priority can occur as well.

Reg 10,11 IMRA,IMRB Interrupt Mask Register

Individual interrupt sources switched on by IER can be masked with the help of this register. That means that the interrupt is recognized from within and is signaled in the IPR, even if the IRQ line remains high.

Reg 12 VR Vector Register

In the cases of interrupts, the 68901 can generate a vector number corresponding to the interrupt source requested by the processor during an Interrupt Acknowledge Cycle. All 16 interrupt channels have their own vectors, with their priorities coded into the bottom four bits of the vector number (the upper four bits of the vector are copied from the vector register). These bits must be set into VR, therefore.

Bit 3 of VR is the previously mentioned S-bit. If this bit is set (like in the ST), then the MFP operates in "Software End-of- Interrupt" mode; a cleared bit puts the system into "Automatic End-of-Interrupt" mode.

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Reg 13,14 TACR,TBCR Timer A/B Control Register

Before proceeding with these registers, we should talk for a moment about the timer. Timers A and B are both identical. Every timer consists of a data register, a programmable feature and an 8-bit count-down counter. Contents of the counters will decrease by one every impulse. When the counter stands at 01, the next impulse changes die corresponding timer to the output of its pins. At the same time, the value of the timer data register is loaded into the timer. If this channel is set by the IER bit, the interrupt will be requested. The source of the timer beats will usually be those quartz frequencies from XTAL1 and 2. This operating mode is called delay mode, and is available to timers C and D.

Timers A and B can also be fed external impulses using timer inputs TAI and TBI (in event count mode). The maximum frequency on timer inputs should not surpass 1/4 of the MFP's operating frequency (that is, 1 mHz).

Another peculiarity of this operating mode is the fact that the timer inputs for the interrupts are I/O pins 13 and 14. By programming the corresponding bits in the AER, a pin-jump can be used by the timer inputs to request an interrupt. TAI is joined with pin 13, TBI by pin 14. Pins 13 and 14 can also be used as I/O lines without interrupt capability.

Timers A and B have yet a third operating mode (pulse-length measurement). This is similar to Delay Mode, with the difference that the timer can be turned on and off with TAI and TBI. Also, when pins 13 and 14 are used, the AER-bits can determine whether the timer inputs are high or low. If, say, AER-bit 4 is set, the counter works when TAI is high. When TAI changes to low, an interrupt is created.

Now we come to TACR and TBCR. Both registers only use the fifth through eighth bits. Bits 0 to 3 determine the operating mode of each timer:

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BIT 3210

Function

0000 Timer stop, no function executed 0001 Delay mode, subdivider divides by 4 0010 Delay mode, subdivider divides by 10 0011 Delay mode, subdivider divides by 16 0011 Delay mode, subdivider divides by 16 0100 Delay mode, subdivider divides by 50 0101 Delay mode, subdivider divides by 64 0110 Delay mode, subdivider divides by 100 0111 Delay mode, subdivider divides by 200 1000 Event Count Mode

1	0	0	1	Pulse	extension	mode, subdivider	divides	by	4
1	0	1	0	Pulse	extension	mode, subdivider	divides	by	10
1	0	1	1	Pulse	extension	mode, subdivider	divides	by	16
1	1	0	0	Pulse	extension	mode, subdivider	divides	by	50
1	1	0	1	Pulse	extension	mode, subdivider	divides	by	64
1	1	1	0	Pulse	extension	mode, subdivider	divides	by	100
1	1	1	1	Pulse	extension	mode, subdivider	divides	by	200

Bit 4 of the Timer Control Register has a particular function. This bit can produce a low reading for the timer being used with it at any time. However, it will immediately go high when the timer runs.

Reg 15 TCDCR Timers C and D Control Register

Timers C and D are available only in delay mode; thus, one byte controls both timers. The control information is programmed into the lower three bits of the nibbles (four- bit halves). Bits 0 and 2 arrange Timer D, Timer C is influenced by bits 4 and 6. Bits 3 and 7 in this register have no function.

2	1	0	Function - Timer D
6	5	4	Function - Timer C
0	0	0	Timer	Stop
0	0	1	Delay	Mode, division	by	4
0	1	0	Delay	Mode, division	by	10
0	1	1	Delay	Mode, division	by	16
1	0	0	Delay	Mode, division	by	50
1	0	1	Delay	Mode, division	by	64
1	1	0	Delay	Mode, division	by	100
1	1	1	Delay	Mode, division	by	200

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Reg 16-19 TADR,TBDR,TCDR,TDDR Timer Data Registers

The four Timer Data Registers are loaded with a value from the counter. When a condition of 01 is reached, an impulse occurs. A continuous countdown will stem from this value.

Reg 20 SCR Synchronous Character Register

A value will be written to this register by synchronous data transfer, so that the receiver of the data will be alerted. When synchronous mode is chosen, all characters received will be stored in the SCR, after first being put into the receive buffer.

Reg 21 UCR,USART Control Register

USART is short for Universal Synchronous/Asynchronous Receiver/Transmitter. The UCR allows you to set all the operating parameters for the interfaces. Parameters can also be coded in with the timers.

Bit 0 : unused

Bit 1 : 0=Odd parity

l=Even parity

Bit 2 : 0=No parity (bit 1 is ignored)

l=Parity according to bit 1

Bits 3,4 : These bis control the number of

start- and stopbits and the format desired.

Bit 4 3 Start Stop Format

000 0 Synchronous

011 1 Asynchronous

10 1 1,5 Asynchronous

111 2 Asynchronous

Bits 5,6 : These bits give the

"wordlength" of the data bits to be transferred.

Bits 6 5 Word length 008 bits 017 bits 106 bits 115 bits

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Bit 7 : 0=Frequency from TC and RC

directly used as transfer frequency (used only for synchronous transfer) l=Frequency in TC and RC internally divided by 16.

Reg 22 RSR Receiver Status Register

The RSR gives information concerning the conditions of all receivers. Again, the different conditions are coded into individual bits.

Bit 0 Receiver Enable Bit

When this bit is cleared, receipt is immediately turned off. All flags in RSR are automatically cleared. A set bit means that the receiver is behaving normally.

Bit 1 Synchronous Strip Enable

This bit allows synchronous data transfer to determine whether or not a character in the SCR is identical to a character in the receive buffer.

Bit 2 Match/Character in Progress

When in synchronous transfer format, this bit signals that a character identical with the SCR byte would be received. In asynchronous mode, this bit is set as soon as the startbit is recognized. A stopbit automatically clears this bit.

Bit 3 Found - Search/Break Detected

This bit is set in synchronous transfer format, when a character received coincides with one stored in the SCR. This condition can be treated as an interrupt over the receiver's error channel. Asynchronous mode will cause the bit to set when a BREAK is received. The break condition is fulfilled when only zeroes are received following a startbit. To distinguish between a BREAK from a "real" null, this line should be low.

Bit 4 Frame Error

A frame error occurs when a byte received is not a null, but the stopbit of the byte IS a null.

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Bit 5 Parity Error

The condition of this bit gives information as to whether parity on the last received character was correct. If the parity test is off, the PE bit is untouched.

Bit 6 Overrun Error

This bit will be set when a complete character is in the receiver floating range but not read into the receive buffer. This error can be operated as an interrupt.

Bit 7 Buffer Full

This bit is set when a character is transferred from the floating register to the receive buffer. As soon as the processor reads the byte, the bit is cleared.

Reg 23 TSR Transmitter Status Register

Whereas the RSR sends receiver information, the TSR handles transmission information.

Bit 0 Transmitter Enable

The sending section is completely shut off when this bit is cleared. At the same time the End-bit is cleared and the UE- bit is set (see below). The output to the receiver is set in the corresponding H- and L-bits.

Bits 1,2 High- and Low-bit

These bits let the programmer decide which mode of output the switched-off transmitter will take on. If both bits are cleared, the output is high. High-bit only will create high output; low-bit, low output. Both bits on will switch on loop-back-mode. This state loops the output from the transmitter with receiver input. The output itself is on the high-pin.

Bit 3 Break

The break-bit has no function in synchronous data transfer. In asynchronous mode, though, a break condition is sent when the bit is set.

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Bit 4 End of Transmission

If the sender is switched off during running transmission, the end-bit will be set as soon as the current character has been sent in its entirety. When no character is sent, the bit is immediately set.

Bit 5 Auto Turnaround

When this bit is set, the receiver is automatically switched on when the transmitter is off, and a character will eventually be sent.

Bit 6 Underrun Error

This bit is switched on when a character in the sender floating register will be sent, before a new character is written into the send buffer.

Bit 7 Buffer Empty

This bit will be set when a character from the send buffer will be transferred to the floating register. The bit is cleared when new data is written to the send buffer.

Reg 24 UDR, USART Data Register

Send/receive data is sent over this register. Writing sends data in the send buffer, reading gives you the contents of the receive buffer.

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1.5 The 6850 ACIAs

ACIA is short for "Asynchronous Communications Interface Adapter". This 24-pin IC has all the components necessary for operating a serial interface, as well as error-recognizing and data-formatting capabilities. Originally for 6800-based computers, this chip can be easily tailored for 6502 and 68000 systems. The ST has two of these chips. One of them communicates with the keyboard, mouse, joystick ports, and runs the clock. Keyboard data travels over a serial interface to the 68000 chip. The second ACIA is used for operating the MIDI interface.

Parameter changes in the keyboard ACIA are not recommended: The connection between keyboard and ST can be easily disrupted. The MIDI interface is another story, though — we can create all sorts of practical applications. Incidentally, nowhere else has it been mentioned that the MIDI connections can be used for other purposes. One idea would be to use the MIDI interfaces of several STs to link them together (for schools or offices, for example).

1.5.1 The Pins of the 6850

For those of you readers who aren't very well-acquainted with the principles of serial data transfer, we've included some fairly detailed descriptions in the pin layout which follows.

Vss

This connection is the "ground wire" of the IC.

RX DATA Receive Data

This pin receives data; a start-bit must precede the least significant data-bit before receipt.

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RX CLK Receive Clock

This pin signal determines baud-rate (speed at which the data is received), and is synchronize to the incoming data. The frequency of RX CLK is patterned after the desired transfer speed and after the internally programmed division rate.

TX CLK Transmitter Clock

Like RX CLK, only used for transmission speed.

RTS Request To Send .

This output signals the processor whether the 6850 is low or high; mostly used for controlling data transfer. A low output will, for example, signal a modem that the computer is ready to transmit.

TX DATA Transmitter Data

This pin sends data bit-wise (serially) from the computer.

IRQ Interrupt Request

Different circumstances set this pin low, signaling the 68000 processor. Possible conditions include completed transmission or receipt of a character.

CS 0,1,2 Chip Select rT,i , . ,

These three lines are needed for ACIA selection. The relatively high number of CS signals help minimize the amount of hardware needed for address decoding, particularly in smaller computer systems.

RS Register Select

This signal communicates with internal registers, and works closely with the R/W signal. We shall talk about these registers later.

Vcc Voltage ,

This pin is required of all ICs - this pin gets an operating voltage

of 5V.

R/W Read/Write ,

This tells the processor the "direction” of data traveling through the ACIA. A high signal tells the processor to read data, and low writes data in the 6850.

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E Enable

The E-signal determines the time of reading/writing. All read/write processes with this signal must be synchronous.

DO - D7 Data

These data lines are connected to those of the 68000. Until the ACIA is accessed, these bidirectional lines are all high.

DCD Data Carrier Detect

A modem control signal, which detects incoming data. When DCD is high, serial data cannot be received.

CTS Clear To Send

CTS answers the computer on the signal RTS. Data transmission is possible only when this pin is low.

1.5.2 The Registers of the 6850

The 6850 has four different registers. Two of these are read only. Two of them are write only. These registers are distinguished by R/W and RS, after the table below:

- Register _ ap.cpss

0 0 Control Register write

0 1 Sender Register write

1 0 Status Register read

1 1 Receive Register read

The sender/receiver registers (also known as the RX- and TX- buffers) are for data transfer. When receiving is possible, the incoming bits are put in a shift register. Once the specified number of bits has arrived, the contents of the shift register are transferred to the TX buffer. The sender works in much the same way, only in the reverse direction (RX buffer to sender shift register).

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The Control Register

The eight-bit control register determines internal operations. To solve the problem of controlling diverse functions with one byte, single bits are set up as below:

CR 0,1 J

These bits determine by which factor the transmitter and receiver clock will be divided. These bits also are joined with a master reset function. The 6850 has no separate reset line, so it must be accomplished through software.

CRl CRO

0 0 RXCLK/TXCLK without division

0 1 RXCLK/TXCLK by 16 (for MIDI)

1 0 RXCLK/TXCLK by 64 (for keyboard)

1 1 Master RESET

These so-called Word Select bits tell whether 7 or 8 data-bits are involved; whether 1 or 2 stop-bits are transferred; and the type of parity.

CR4

0

1

CR3 CR2 0 0

0 1

1 0

1 1

0 0

0 1

1 0

1 1

7 databits, 7 databits, 7 databits,

7 databits,

8 databits, 8 databits, 8 databits, 8 databits.

2 stopbits, 2 stopbits, 1 stopbit,

1 stopbit,

2 stopbit,

1 stopbit,

1 stopbit.

even parity odd parity even parity odd parity no parity no parity even parity odd parity

These Transmitter Control bits set the RTS output pin, and allow or prevent an interrupt through the ACIA when the send register is emptied. Also, BREAK signals can be sent over the serial output by this line. A BREAK signal is nothing more than a long sequence of null bits.

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CR6

0

1

CR5

0 RTS low, transmitter IRQ disabled

1 RTS low, transmitter IRQ enabled

0 RTS high, transmitter IRQ disabled

1 RTS low, transmitter IRQ disabled, BREAK

sent

CR 7

The Receiver Interrupt Enable bit determines whether the receiver interrupt will be on. An interrupt can be caused by the DCD line changing from low to high, or by the receiver data buffer filling. Besides that, an interrupt can occur from an OVERRUN (a received character isn't properly read from the processor).

CR7

0 Interrupt disabled

1 Interrupt enabled

The Status Register

The Status Register gives information about the status of the chip. It also has its information coded into individual bytes.

SRO

When this bit is high, the RX data register is full. The byte must be read before a new character can be received (otherwise an OVERRUN happens).

SRI

This bit reflects the status of the TX data buffer. An empty register sets the bit.

SR2

A low-high change on pin DCD sets SR2. If the receiver interrupt is allowable, the IRQ will be cancelled. The bit is cleared when the status register and the receiver register are read. This also cancels the IRQ. SR2 register remains high if the signal on the DCD pin is still high; SR2 registers low if DCD becomes low.

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SR3

This line shows the status of CTS. This signal cannot be altered by a master reset, or by ACIA programming.

SR4

Shows "Frame errors". Frame errors are when no stop-bit is recognized in receiver switching. It can be set with every new character.

This bit displays the previously mentioned OVERRUN condition. SR5 is reset when the RX buffer is read.

SR6

This bit recognizes whether the parity of a received character is correct. The bit is set on an error.

This signals the state of the IRQ pins; this bit makes it possible to switch several IRQ lines on one interrupt input. In cases where an interrupt is program-generated, SR7 can tell which IC cut off the interrupt.

The ACIAs in the ST

The ACIAs have lots of extras unnecessary to the ST. In fact, CTS, DCD and RTS are not connected.

The keyboard ACIA lies at the addresses $FFFC00 and $FFFC02. Built-in parameters are: 8-bit word, 1 stopbit, no parity, 7812.5 baud (500 kHz/64).

The parameters are the same for the MIDI chip, EXCEPT for the baud rate, which runs at 31250 baud (500 kHz/16).

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1.6 The YM-2149 Sound Generator

The Yamaha YM-2149, a PSG (programmable sound generator) in the same family as the General Instruments AY-3-8190, is a first-class sound synthesis chip. It was developed to produce sound for arcade games. The PSG also has remarkable capabilities for generating/altering sounds. Additionally, the PSG can be easily controlled by joysticks, the computer keyboard, or external keyboard switching. The PSG has two bidirectional 8-bit parallel ports. Here's some general data on the YM-2149:

• three independently programmable tone generators

• a programmable noise generator

• complete software-controlled analog output

• programmable mixer for tone/noise

• 15 logarithmically raised volume levels

• programmable envelopes (ASDR)

• two bidirectional 8-bit data ports

• TTL-compatible

• simple 5-volt power

The YM-2149 has a total of 16 registers. All sound capabilities are controlled by these registers.

The PSG has several "functional blocks" each with its own job. The tone generator block produces a square-wave sound by means of a time signal. The noise generator block produces a frequency-modulated square-wave signal, whose pulse- width simulates a noise generator. The mixer couples the three tone generators’ output with the noise signal. The channels may be coupled by programming.

The amplitude control block controls the output volume of the three channels with the volume registers; or creates envelopes (Attack, Decay, Sustain, Release, or ADSR), which controls the volume and alters the sound quality.

The D/A converter translates the volume and envelope information into digital form, for external use. Finally one function block controls the two I/O ports.

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1.6.1 Sound Chip Pins

Vss:

This is the PSG ground connection.

NC.:

Not used.

ANALOG B:

This is the channel B output. Maximum output voltage is 1 vss. ANALOG A:

Works like pin 3, but for channel A.

NC.:

Not used.

IOB7 - 0:

The IOB connections make up one of the two 8-bit ports on the chip. These pins can be used for either input or output. Mixed operation (input and output combined) is impossible within one port, however both ports are independent of one another.

IOA7 - 0:

Like IOB, but for port A.

CLOCK:

All tone frequencies are divided by this signal. This signal operates at a frequency between 1 and 2 mHz.

RESET:

A low signal from this pin resets all internal registers. Without a reset, random numbers exist in all registers, the result being a rather unmusical "racket".

A9:

This pin acts as a chip select-signal. When it is low, the PSG registers are ready for communication.

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A8:

Similar to A9, only it is active when high.

TEST2:

Test2 is used for testing in the factory, and is unused in normal operation.

BDIR & BC1,2:

The BDIR (Bus DIRection), BC1 and BC2 (Bus Control) pins control the PSG’s register access.

BDIR BC2 BC1

0 0 0

0 0 1

0 10

Oil 10 0 10 1 110 111

PSG function Inactive Latch address Inactive Read from PSG Latch address Inactive Write to PSG Latch address

Only four of these combinations are of any use to us; those with a 5+ voltage running over BC2. So, here's what we have left:

BDIR BC1 Function

0 0 Inactive, PSG data bus high

0 1 Read PSG registers

1 0 Write PSG registers

1 1 Latch, write register number (

s)

DAO - 7:

These pins connect the sound chip to the processor, through the data bus. The identifier DA means that both data and (register) addresses can be sent over these lines.

ANALOG C:

Works with channel C (see ANALOG B, above).

TEST1:

See TEST2.

Ycc:

+5 volt pin.

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1.6.2 The 2149 Registers and their Functions

Now let's look at the functions of the individual registers. One point of interest: the contents of the address register remain unaltered until reprogrammed. You can use the same data over and over, without having to send that data again.

Reg 0,1:

These register determine the period length, and the pitch of ANALOG A. Not all 16 bits are used here; the eight bits of register 0 (set frequency) and the four lowest bits of register 1 (control step size). The lower the 12-bit value in the register, the higher the tone.

Reg 2,3:

Same as registers 0 and 1, only for channel B.

Reg 4,5:

Same as registers 0 and 1, only for channel C.

Reg 6:

The five lowest bits of this register control the noise generator. Again, the smaller the value, the higher the noise "pitch".

Reg 7:

Bit	0 : Channel	A tone on/off	0=on	/ l=of f
Bit	1 : Channel	B tone on/off	0=on	/ 1— of f
Bit	2 : Channel	C tone on/off	0=on	/ l=of f
Bit	3 : Channel	A noise on/off	0=on	/ l=of f
Bit	4 : Channel	B noise on/off	0=on	/ l=of f
Bit	5 : Channel	C noise on/off	0=on	/ l=of f
Bit	6: Port A	in/ output	0=in	/ l=out
Bit	7 : Port B	in/ output	0=in	/l=out

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Figure 1.6-2 Envelopes of the PSG

REG 15

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Reg 8:

Bits 0-3 of this register control the signal volume of channel A. When bit 4 is set, the envelope register is being used and the contents of bits 0-3 are ignored.

Reg 9:

Same as register 8, but for channel B.

Reg 10:

Same as register 8, but for channel C.

Reg 11,12:

The contents of register 1 1 are the low-byte and the contents of register 12 are the high-byte of the sustain.

Reg 13:

Bits 0-3 determine the waveform of the envelope generator. The possible envelopes are pictured in Figure 1.6-2.

Reg 14,15:

These registers comprise the two 8-bit ports. Register 14 is connected to Port A and register 15 is connected to Port B. If these ports are programmed as output (bits 7 and 8 of register 7) then values may be sent through these registers.

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1.7 I/O Register Layout in the ST

The entire I/O range (all peripheral ICs and other registers) is controlled by a 32K address register - $FF8000 - $FFFFFF. Below is a complete table of the different registers. CAUTION: The I/O section can be accessed only in supervisor mode. Any access in user mode results in a bus-error.

$FF8000 Memory configuration $FF8200 Video display register $FF8400 Reserved $FF8600 DMA/disk controller $FF8800 Sound chip $FFFA00 MFP 68901

$FFFC00 ACIAs for MIDI and keyboard

The addresses given refer only to the start of each register, and supply no hint as to the size of each. More detailed information follows.

$FF8000 Memory Configuration

There is a single 8-bit register at $FF8001 in which the memory configuration is set up (four lowest bits). The MMU-IC is designed for maximum versatility within the ST. It lets you use three different types of memory expansion chips: 64K, 256K, and the 1M chips. Since all of these ICs are bit-oriented instead of byte-oriented, 16 memory chips of each type are required for memory expansion. The identifier for 16 such chips (regardless of memory capacity) is BANK. So, expansion is possible to 128 Kbyte, 512 Kbyte or even 2 Megabytes.

MMU can control two banks at once, using the RAS- and CAS- signals. The table on the next page shows the possible combinations:

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SFF8001

Bit _ Memory configuration

3-0 Bank 0 Bank 1

0000	128K
0001	128K
0010	128K
0011	reserved
0100	512K
0101	512K
0100	512K
0100	reserved
1000	2M
1001	2M
1010	2M
1011	reserved
11XX	reserved

128K 512K 2 M

128K

512K

2 M, normally reserved

128K

512K

2M

The memory configuration can be read from or written to.

$ff§2QQ _ YifleQ Pisplay Register

This register is the storage area that determines the resolution and the color palette of the video display.

$FF8201 8-bit Screen memory position (high-byte)

$FF8203 8-bit Screen memory position (low-byte)

These two read/write registers are located at the beginning of the 32K video RAM.

In order to relocate video RAM, another register is used. This register is three bytes long and is located at $FF8205. Video RAM can be relocated in 256-byte increments. Normally the starting address of video RAM is $78000.

$FF8205 $FF8207 $FF820 9

8-bit

Video address Video address Video address

pointer

(high-byte)

(mid-byte)

(low-byte)

These three registers are read only. Every three microseconds, the contents of these registers are incremented by 2.

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$FF820A BIT Synchronization mode

1 0

: 0=internal, l=external synchronization

: - 0=60 Hz , l=50Hz screen frequency

The bottom two bits of this register control synchronization mode; the remaining bits are unused. If bit 0 is set, the HSync and VSync impulses are shut off, which allows for screen synchronization from external sources (monitor jack). This offers new realm of possibilities in video, synchronization of your ST and a video camera, for example.

Bit 1 of the sync-mode register handles the screen frequency. This bit is useful only in the two "lowest" resolutions. High-res operation puts the ST at a 70 Hz screen frequency.

Sync mode can be read/written.

$FF8240 16-bit $FF8242 16-bit

$FF825C 16-bit $FF825E 16-bit

Color palette register 0 Color palette register 1

Color palette registers 2-13

Color palette register 14 Color palette register 15

Although the ST has a total of 512 colors, only 16 different colors can be displayed on the screen at one time. The reason for this is that the user has 16 color pens on screen, and each can be one of 512 colors. The color palette registers represent these pens. All 16 registers contain 9 bits which affect the color:

FEDCBA987 654 3210 . XXX . XXX . XXX

The bits marked X control the registers. Bits 0-2 adjust the shade of blue desired; 4-6, green hue; and 8- A, red. The higher the value in these three bits, the more intense the resulting color.

Middle resolution (640 X 200 points) offers four different colors; colors 4 through 15 are ignored by the palette registers.

When you want the maximum of 16 colors, it's best to zero-out the contents of the palette registers.

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High-res (640 X 400 points) gives you a choice on only one "color"; bit 0 of palette register 0 is set to the background color. If the bit is cleared, then the text is black on a light background. A set bit reverses the screen (light characters, black background). The color register is a read/write register.

$FF82 60

Bit Resolution 1 0

0 0 320 X 200 points, four focal planes

0 1 640 X 200 points, two focal planes

1 0 640 X 400 points, one focal planes

This register sets up the appropriate hardware for the graphic resolution desired.

SFFStiQQ _ DMA/Disk Controller

$FF8600 reserved

$FF8602 reserved

$FF8604 16-bit FDC access/sector count

The lowest 8 bits access the FDC registers. The upper 8 bits contain no information, and consistently read 1. Which register of the FDC is used depends upon the information in the DMA mode control register at $FF8606. The FDC can also be accessed indirectly.

The sector count-register under $FF8604 can be accessed when the appropriate bit in the DMA control register is set. The contents of these addresses are both read/write.

$FF8606 16-bit DMA mode/status

When this register is read, the DMA status is found in the lower three bits of the register.

Bit 0 0=no error, 1=DMA error

Bit 1 0 = sector count = null, l=sector countonull

Bit 2 Condition of FDC DATA REQUEST signal

Write access to this address controls the DMA mode register.

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Bit 0 unused

Bit 1 0=pin AO is low

l=pin AO is high

Bit 2 0=pin A1 is low

l=pin A1 is high

Bit 3 0=FDC access

1=HDC access

Bit 4 0=access to FDC register

l=access to sector count register Bit 5 0 , reserved

Bit 6 0=DMA on

l=no DMA

Bit 7 0=hard disk controller access (HDC)

1=FDC access

Bit 8 0=read FDC/HDC registers

l=write to FDC/HDC registers

$FF8609 8-bit $FF8 60B 8-bit $FF8 60D 8-bit

DMA basis and counter DMA basis and counter DMA basis and counter

high-byte

mid-byte

low-byte

DMA transfer will tell the hardware at which address the data is to be moved. The initialization of the three registers must begin with the low-byte of the address, then mid-byte, then high-byte.

$FF88QQ SquM-Que

The YM-2149 has 16 internal registers which can't be directly addressed. Instead, the number for the desired register is loaded into the select register. The chosen registers can be read/write, until a new register number is written to the PSG.

$FF8800 8-bit Read data/Register select

Reading this address gives you the last register used (normally port A), by which disk drive is selected. This can be accomplished with write-protect signals, although these protected contents can be accessed by another register. Port A is used for multiple control functions, while port B is the printer data port.

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PORT A Bit 0

Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

Page-choice signal for double-sided floppy drive

Drive select signal — floppy drive 0 Drive select signal — floppy drive 1 RS-232 RTS-output RS-232 DTR output Centronics strobe

Freely usable output (monitor jack) reserved

When $FF8800 is written to, the select register of the PSG is alerted. The information in the bottom four bits are then considered as register numbers. The necessary four-bit number serves for writing to the PSG.

$FF8802 8-bit Write data

Attempting to read this address after writing to it will give you $FF only, while BDIR and BC1 are nulls.

Writing register numbers and data can be performed with a single MOVE instruction.

$FFFAQ0 _ MFP 689Q1

The MFP's 24 registers are found at odd addresses from $FFFA01-$FFFA2F:

$FFFA0 1	8-bit	Parallel port
$FFFA03	8-bit	Active Edge register
$FFFA05	8-bit	Data direction
$FFFA07	8-bit	Interrupt	enable A
$FFFA0 9	8-bit	Interrupt	enable B
$FFFA0B	8-bit	Interrupt	pending A
$FFFA0D	8-bit	Interrupt	pending B
$FFFA0F	8-bit	Interrupt	in-service A
$FFFA1 1	8-bit	Interrupt	in-service B
$FFFA13	8-bit	Interrupt	mask A
$FFFA15	8-bit	Interrupt	mask B
$FFFA17	8-bit	Vector register
$FFFA1 9	8-bit	Timer A control
$FFFA1B	8-bit	Timer B control

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$FFFA1D	8-bit	Timer	C & D control
$FFFA1F	8-bit	Timer	A data
$FFFA2 1	8-bit	Timer	B data
$FFFA23	8-bit	Timer	C data
$FFFA2 5	8-bit	Timer	D data
$FFFA2 7	8-bit	Sync i	character
$FFFA2 9	8-bit	USART	control
$FFFA2B	8-bit	Receiver status
$FFFA2D	8-bit	Transmitter status
$FFFA2F	8-bit	USART	data

See the chapter on the MFP for details on the individual registers.

I/O Port Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

Centronics busy

RS-232 data carrier detect - input RS-232 clear to send - input reserved

keyboard and MIDI interrupt FDC and HDC interrupt RS-232 ring indicator Monochrome monitor detect

Timers A and B each have an input which can be used by external timer control, or send a time impulse from an external source. Timer A is unused in the ST, which means that the input is always available, but it isn't connected to the user port, so the Centronics busy pin is connected instead. You can use it for your own purposes.

Timer B is used for counting screen lines in conjunction with DE (Display Enable).

The timer outputs in A-C are unused. Timer D, on the other hand, sends the timing signal for the MFP's built-in serial interface.

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SFFFCOO Keyboard and MIDI ACIAs

The communications between the ST, the keyboard, and musical instruments are handled by two registers in the ACIAs.

$FFFC0 0 8-bit $FFFC02 8-bit $FFFC0 4 8-bit $FFFC0 6 8-bit

Keyboard ACIA control Keyboard ACIA data MIDI ACIA control MIDI ACIA data

Figure 1.7-1 I/O Assignments

SFFFCOO

SFFFAOO

2 ACIA* s 6580

MFP 68901

SFF8800

$FF8600

SFF8400

SFF8200

SFF8000

SOUND AY-3-8910

DMA / WD 1770

RESERVED

VIDEO CONTROLLER

DATA CONFIGURATION

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Figure 1.7-2 Memory Map of the ATARI ST

$FF FCOO

$FF FHOO

$FF 8800 8600 8400 8200 $FF 8000

16776192

16775680

16746496

16745984

16745472

16744960

16744448

$FE FFFF

$FC 0000

$Ffi 0000

$07 FFFF

$00 0000

192 K

System ROM

128 K ROM Expansion Cartridge

16711679

16515072

16384000

524287

0

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BLOCK DIAGRAM of the ATARI ST

64

6850

Chapter Two

The Interfaces

2.1 The Keyboard

2.1.1 The Mouse

2.1.2 Keyboard commands

2.2 The Video Connection

2.3 The Centronics Interface

2.4 The RS-232 Interface

2.5 The MIDI Connections

2.6 The Cartridge Slot 2.6.1 ROM Cartridges

2.7 The Floppy Disk Interface

2.8 The DMA Interface

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The Interfaces

2.1 The Keyboard

Do you think it's really necessary to give a detailed report on something as trivial as the keyboard, since keyboards all function the same way? Actually the title should read "Keyboard Systems" or something similar. The keyboard is controlled by its own processor. You will soon see how this affects the assembly language programmer.

The keyboard processor is single-chip computer (controller) from the 6800 family, the 6301. Single chip means that everything needed for operation is found on a single IC. In actuality, there are some passive components in the keyboard circuit along with the 6301.

The 6301 has ROM, RAM, some I/O lines, and even a serial interface on the chip. The serial interface handles the traffic to and from the main board.

The advantage of this design is easy to see. The main computer is not burdened by having to continually poll the keyboard. Instead it can dedicate itself completely to processing your programs. The keyboard processor notifies the system if an event occurs that the operating system should be aware of.

The 6301 is not only responsible for the relatively boring task of reading the keyboard, however. It also takes care of the rather complicated tasks required in connection with the mouse. The main processor is then fed simply the new X and Y coordinates when the mouse is moved. Naturally, anything to do with the joysticks is also taken care of by the keyboard controller.

In addition, this controller contains a real-time clock which counts in one-second increments.

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In Figure 2.1-1 is an overview of the interface to the 68000. As you see, the main processors is burdened as little as possible. The ACIA 6850 ensures that it is disturbed only when a byte has actually been completely received from the keyboard. The ACIA, by the way, can be accessed at addresses $FFFC00 (control register) and $FFFC02 (data register). The individual connection to the keyboard takes place over lines K14 and K15. K indicates the plug connection by which the keyboard is connected to the main board.

The signal that the ACIA has received a byte is first sent over line 14 to the MFP 68901 which then generates an interrupt to the 68000. The clock frequency of 500KHz comes from GLUE. From this results the "odd" transfer rate of 7812.5 baud.

In case you were surprised that data can also be sent to the keyboard processor, you will find the solution to the puzzle in Chapter 2.1.2.

The block diagram of the keyboard circuit is found in Figure 2.1-2. The function is as simple as the figure is easy to read. The processor has 4K of ROM available. The 128 bytes of RAM is comparatively small, but it is used only as a buffer and for storing pointers and counters.

The lines designated with K are again the plug connections assigned to the main board. With few exceptions, the connections for the joystick and mouse are also put through. K 16 is the reset line from the 68000. K15 carries the send data from the 6850, K14 the send data from the 6301.

The I/O ports 1(0-7), 3(1-7), and 4(0-7) are responsible for reading the keyboard matrix. One line from ports 3 and 4 is pulled low in a cycle. The state of port 1 is the checked. If a key is pressed, the low signal comes through on port 1.

Each key can be identified from the combination of value placed on ports 3 and 4 and the value read from port 1.

If none of the lines of Port 3 and 4 are placed low and a bit of port 1 still equals zero, a joystick is active on the outer connector 1. The data from outer connector 0, to which a mouse or a joystick can be connected, does not come through by chance since it must first be switched through the NAND gate with port 2 (bit 0). The buttons on the mouse or the joystick then arrive at port 2 (1 and 2).

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Figure 2.1-2 Block Diagram of Keyboard Circuit

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The assignments of the K lines to the signal names on the outer connector are found in the next section.

The 6301 processor is completely independent, but it can also be configured so that it works with an external ROM. Some of the port lines are then reconfigured to act as address lines. The configuration the processor assumes (one of eight possibilities) depends on the logical signal placed on port 2 (bits 0-2) during the reset cycle. All three lines high puts the processor in mode 7, the right one for the task intended here. But bits 1 and 2 depend on the buttons on the mouse. If you leave the mouse alone while powering-up, everything will be in order. If you hold the two buttons down, however, the processor enters mode 1 and makes a magnificent belly-flop, since the hardware for this operating mode is not provided. You notice this by the fact that the mouse cursor does not move on the screen if you move the mouse. Only the reset button will restore the processor.

2.1.1 The Mouse

The construction of this little device is quite simple, but effective. Essentially, it consists of four light barriers, two encoder wheels, and a drive mechanism.

The task of the mouse is to give the computer information about its movements. This information consists of the components: direction on the X-axis, direction on the Y-axis, and the path traveled on each axis.

In order to do this, the rubber-covered ball visible from the outside drives two encoder wheels whose drive axes are at angle of 90 degrees to each other. The one or the other axis rotates more or less, forwards or backwards, depending on the direction the mouse is moved.

It is no problem to determine the absolute movement on each axis. The encoder wheels alternately interrupt the light barriers. One need only count the pulses from each wheel to be informed about the path traveled on each axis.

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It is more difficult when the direction of movement is also required. The designers of the mouse used a convenient trick for this. There are not one, but two light barriers on each encoder wheel. They are arranged such that they are not shielded by the wheel at precisely the same time, but one shortly after the other. This arrangement may not be so clear in Figure 2. 1.1-1, so we’ll explain it in more detail The direction can be determined by noticing which of the two light barriers is interrupted first. This is why the pulses from both light barriers are sent out, making a total of four. Corresponding to their significance they carry the names XA, XB, YA, YB.

The two contacts which you see on the picture represent the two buttons.

The large box on the picture is a quad operational amplifier which converts the rather rough light-barrier pulses into square wave signals.

In Figure 2. 1.1 -2 is the layout of the control port on the computer, as you see it when you look at it from the outside. The designation behind the slash applies when a joystick is connected and the number in parentheses is the pin number of the keyboard connector.

PortO

1	XB/UP	(K12)
2	XA/DOWN	(K10)
3	YA/LEFT	(K9)
4	YB/RIGHT	(K8)
6	LEFT BUTTON/FIRE	(Kll)
7	+5V	(K13)
8	GND	(Kl)
9	RIGHT BUTTON	(K6)
Port 1
1	UP	(K7)
2	DOWN	(K5)
3	LEFT	(K4)
4	RIGHT	(K3)
5	Port 0 enable	(K17)
6	FIRE	(K6)
7	+5V	(K13)
8	GND	(Kl)

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Figure 2.1. 1-2 Mouse control port

1 5

6 9

2.1.2 Keyboard commands

The keyboard processor "understands" some commands pertaining to such things as how the mouse is to be handled, etc. You can set the clock time, read the internal memory, and so on. You can find an application example in the assembly language listing on page 80 (after command $21).

The "normal" action of the processor consists of keeping an eye on the keyboard and announcing each keypress. This is done by outputting the number of the key when the key is pressed. When the key is released the number is set again, but with bit 7 set. The result of this is that no key numbers greater than 127 are possible. You can find the assignment of the key numbers to the keys at the end of this section in figure 2. 1.2-1. In reality these numbers only go up to 117 because values from $F6 up are reserved for other purposes. There must be a way to pass more information than just key numbers to the main processor, information such as the clock time or the current position of the mouse. This cannot be handled in a single byte but only in something called a package, so the bytes at $F6 signal the start of a package. Which header comes before which package is explained along with the individual commands.

A command to the keyboard processor consists of the command code (a byte) and any parameters required. The following description is sorted according to command bytes.

$07

Returns the result of pressing one of the two mouse buttons. A parameter byte with the following format is required:

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Bit 0 =1: Bit 1 =1: Bit 2 =1 :

Bits 3-7

The absolute position is returned when a mouse button is pressed. Bit 2 must =0. The absolute position is returned when a mouse button is released. Bit 2 must — 0 . The mouse buttons are treated like normal keys. The left button is key number $74, the right is $75. must always be zero.

$08

Returns the relative mouse position from now on. This command tells the keyboard processor to automatically return the relative position (the distance from the previous position) whenever the mouse is moved. A movement is given when the number of encoder wheel pulses has reached a given threshold. See also $0B. A relative mouse package looks like this:

1 byte Header in range $F8-$FB. The two lowest

bits of the header indicate the condition of the two mouse buttons .

1 byte Relative X-position (signed!)

1 byte Relative Y-position (signed!)

If the relative position changes substantially between two packages so that the distance can no longer be expressed in one byte, another package is automatically created which makes up for the remainder.

$09

Returns the absolute mouse position from now on. This command also sets the coordinate maximums. The internal coordinate pointers are at the same time set to zero. The following parameters are required.

1 word Maximum X coordinate 1 word Maximum Y-coordinate

Mouse movements under the zero point or over the maximums are not returned.

With this command it is possible to get the key numbers of the cursor ys instead of the coordinates. A mouse movement then appears to the operating system as if the corresponding cursor keys had been pressed. These parameters are necessary:

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1 byte Number of pulses (X) after which the key number for cursor left (or right) will be sent .

1 byte Number of pulses (Y) after which the key

number for cursor up (or down) will be sent.

$0B

This command sets the trigger threshold, above which movements will be announced. A certain number of encoder pulses elapse before a package is sent. This functions only in the relative operating mode. The following are the parameters:

1 byte Threshold in X-direction 1 byte Threshold in Y-direction

$0C

Scale mouse. Here is determined how many encoder pulses will go by before the coordinate counter is changed by 1. This command is valid only in the absolute. The following parameters are required:

1 byte X scaling

1 byte Y scaling

$0D

Read absolute mouse position. No parameters are required, but a package of the following form is sent:

1 byte Header

1 byte Button

Bit 0=1:

Bit 1=1: Bit 2=1:

Bit 3=1:

= $F7 status

Right button was pressed since the last read

Right button was not pressed Left button was pressed since the last read

Left button was not pressed

From this strange arrangement you can determine that the state of a button has changed since the last read if the two bits pertaining to it are zero.

1 word Absolute X-coordinate 1 word Absolute Y-coordinate

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Set the internal coordinate counter. The following parameters are required:

1 byte =0 as fill byte

1 word X-coordinate

1 word Y-coordinate

$0F

Set the origin for the Y-axis is down (next to the user).

$10

Set the origin for the Y-axis is up.

The data transfer to the main processor is permitted again (see $13). Any command other than $13 will also restart the transfer.

Turn mouse off. Any mouse-mode command ($08, $09, $0A) turns the mouse back on. If the mouse is in mode $0A, this command has no effect.

$13

Stop data transfer to main processor.

NOTE: Mouse movements and key presses will be stored as long as the small buffer of the 6301 allows. Actions beyond the capacity of the butter

will be lost.

Every joystick movement is automatically returned. The packages sent have the following format:

1 byte 1 byte

Header = $FE or $FF for joystick 0/1 Bits 0-3 for the position (a bit for each direction) , bit 7 for the button

End the automatic-return mode for the joystick. When needed, a package must be requested with $16.

Read joystick. After this command the keyboard sends a package as described above.

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$17

Joystick duration message. One parameter is required.

1 byte Time between two messages in 1/100 sec.

From this point on, packages of the following form are sent continuously (as long as no other mode is selected):

1 byte Bit 0 for the button on joystick 1, bit 1

for that of joystick 0

1 byte Bits 0-3 for the position of joystick 1,

bits 4-7 for the position of joystick 0

NOTE: The read interval should not be shorter than the transfer channel needs to send the two bytes of the package.

$18

Fire button duration message. The condition of the button in joystick 1 (!) is continually tested and the result packed into a byte. This means that a message byte contains 8 such tests, whereby bit 7 is the most recent. The keyboard controller determines the time between byte fetches by the main processor. This time is divided into eight equal intervals in which the button is polled. The polling then takes place as regularly as possible. This mode remains active until another command is received.

$19

Cursor key simulation mode for joystick 0 (!). The current position of the joystick is sent to the main processor as if the corresponding cursor keys had been pressed (as often as necessary). To avoid having to explain the same things for the following parameters, here are the most important: All times are assumed to be in tenths of seconds. R indicates the time, when reached, cursor clicks will be sent in intervals of T. After this the interval is V. If R=0, only V is responsible for the interval. Naturally, this mechanism comes into play only when the joystick is held in the same position for longer than T or R.

1	byte	RX
1	byte	RY
1	byte	TX
1	byte	TY
1	byte	vx
1	byte	VY

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Turn off joysticks. Any other joystick command turns them on again.

Set clock time. This command sets the internal real-time clock in the keyboard processor. The values are passed in packed BCD, meaning a digit 0-9 for each half byte, yielding a two-digit decimal number per byte. 1 he following parameters are necessary:

Year, two digit (85, 86, etc.)

Month, two digit (12, 01, etc.)

Day, two digit (31,01,02, etc.)

Hours, two digit Minutes, two digit Seconds, two digit

Any half byte which does not contain a valid BCD digit (such as F) is ignored. This makes it possible to change just part of the date or clock time.

Read clock time. After receiving this command the keyboard processor returns a package having the same format as the one described above. A header is added to the package, however, having the value $FC.

1 byte 1 byte 1 byte 1 byte 1 byte 1 byte

Load memory. The internal memory of the keyboard processor (naturally only the RAM in the range $80 to $FF makes sense) can be written with this command. It is not clear to us of what use this is since according to our investigations (we have disassembled the operating system of the 6301), no RAM is available to be used as desired. Perhaps certain parameters can be changed in this manner which are not accessible through legal means. Here are the parameters:

1 word Start address

1 byte Number of bytes (max. 128)

Data bytes (corresponding to the number)

The interval at which the data bytes will be sent must be less than 20 msec.

1

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$21

Read memory. This command is the opposite of $20. These parameters are required:

1 word Address at which to read

A package having the following format is returned:

1 byte Header 1 =$F6. This is the status header

which precedes all packages containing any operating conditions of the keyboard processor. We will come to the general status messages shortly.

1 byte Header 2 =$20 as indicator that this package carries the memory contents.

6 bytes Memory contents starting with the address given in the command.

Here is a small program which we used to read the ROM in the 6301 and output it to a printer. Here you also see how the status packages arrive from the keyboard. These are normally thrown away by the 68000 operating system. Section 3.1 contains information about the GEMDOS and XBIOS calls used.

start :

prt	equ	0
chout	equ	3
gemdos	equ	1
bios	equ	13
xbios	equ	14
stvec	equ	12
rdm	equ	$21
wrkbd	equ	25
kbdvec	equ	34
term	equ	0

move.w fkbdvec, - (a7) trap #xbios

addq.l #2,a7 move . 1 d0,a0

lea keyin.al

move . 1 dO.savea move.l stvec (aO) , save

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loop:

wait :

buf out : by tout :

hexout :

chrout

exit :

move . 1	al, stvec (aO)
move .w	#$f 000 , d4
move .w	d4,tbuf+l
bsr	keyout
cmpi .b	rbuf
beq	wait
moveq.w	#5,d6
bsr	bufout
addq . w	#6,d4
bmi	loop
bra	exit
lea	rbuf+2, a4
move .b	(a4) +, dO
bsr	hexout
dbra	d6, bytout
rts
movea.w	d0,al
lsr .b	#4 , dO
andi .w	#15, dO
lea	table, a3
move .b	0 (a3,d0) ,d2
lsl .w	#8,d2
move . w	al,d0
andi .w	#15, dO
move .b	0 <a3,d0) ,d2
move .w	d2,d0
move .w	d2,-(a7)
lsr .w	=#: CO a o
bsr	chrout
move ,w	(a7) +, dO
bsr	chrout
move .b	#" " , dO
move .w	dO,- (a7)
move . w	#prt, - (a7)
move .w	#chout, - (a7)
trap	#bios
addq . 1	#6,a7
rts
movea	savea, aO
move . 1	save, stvec (aO)

Starting address Current address

Ending address?

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	move . w	Iterm, - (a7)
	trap	tgemdos
keyout :
	move .b	rbuf
	pea	tbuf
	move . w	#2,-(a7)
	move . w	twrkbd, - (a7)
	trap	#xbios
	addq . 1 rts	#8,a7
keyin :
	moveq	#7, dO
	lea	rbuf, al
repin :
	move .b	(aO) + , (al) +
	dbra rts	dO, repin
table :
	dc.b	"012345678 9ABCDEF "
	rbuf :	ds .b 8
	save	ds.l 1
	save a	ds .1 1
	dummy	ds .b 1
	tbuf	dc . b rdm
	ds .b . end	2

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$22 • ■ u

Execute routine. With this command you can execute a subroutine in the 6301. Naturally, you must know exactly what it does and where it is located, so long as you have not transferred it yourself to RAM with $20 (assuming you found some free space). The only required parameters are:

1 word Start address

Status messages

You can at any time read the operating parameters of the keyboard by simply adding $80 to the command byte with which you would to set the operating mode (whose parameters you want to know). You then get a status package back (header- $F6), whose format corresponds exactly to those which would be necessary for setting the operating mode.

An example makes it clearer: you want to know how the mouse is scaled. So you send as the command the value $8C (since $0C sets the scaling). You get the following back:

1 byte Status header =$F6 1 byte X-scaling 1 byte Y-scaling

This is the same format which would be necessary for the command $0C. For commands which do not require parameters, you get the evoked command back as such. For example, say you want to know what operating mode the joystick is in ($14 or $15). You send the value $94 (or $95, it makes no difference). As status package you receive, in addition to the header, either $14 or $15 depending on the operating mode of the joystick handler.

Allowed status checks are: $87, $88, $89, $8A, $8B, $8C, $8F, $90, $92, $94, $99, and $9A.

In conclusion we have a tip for those for whom the functions of the keyboard are too meager and who want to give it more "intelligence . The processor 6301 is also available in "piggy-back" version, the 63P01 (Hitachi). This model does not have ROM built in, but has a socket on the top for an EPROM of type 2732 or 2764 (8K!). You can then realize your own ideas and, for example, use the two joystick connections as universal 4-bit I/O ports, for which you can also extend the command set in order to access the new functions from the XBIOS as well.

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2.2 The Video Connection

Without this, nothing would be displayed. You would be typing blind. You'll notice the many pins on the connection. Naturally more lines are required for hooking up an RGB monitor than for a monochrome screen, but seven would be enough. There is also something special about the remaining lines. In Figure 2.2-1 you find a block diagram in which you can see how the video connection is tied to the system. The numbering of the pins is given on the figure on the next page, as you can see, when you look at the connector from die outside. Here is the pin layout:

1 AUDIO OUT. This connection comes from the amplifier connected to the output of the sound chip. A high-impedance earphone can be attached here if you do not use the original monitor.

2 COMPOSITE VIDEO is the connection from 9-12. This is not available on the early 520ST or 1040 ST.

3 GPO, General Purpose Output. This connection is available for your use. The line has TTL levels and comes from I/O port A bit 6 of the sound chip.

4 MONOCHROME DETECT. If this line, which leads to the 17 input of the MFP 68901, is low, the computer enters the high-resolution monochrome mode. If the state of the line changes during operation, a cold start is generated.

5 AUDIO IN leads to the input of the amplifier described in 1 and is there mixed with the output of the sound chip.

6 GREEN is the analog green output of the video shifter.

7 RED. Red output.

8 +12 control voltage for color televisions with video connectors.

Atari 520ST = GROUND.

9 HORIZONTAL SYNC is responsible for the horizontal beam return of the monitor.

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Figure 2.2-1 Diagram of Video Interface

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10 BLUE is the analog blue output of the video shifter.

11 MONOCHROME provides a monochrome monitor with the intensity signal.

12 VERTICAL SYNC takes care of the beam return at the end of the screen.

13 GROUND.

A tip for the hardware hobbyist:

A plug to fit this connector is not available. If you want to make a plug for connecting other monitors, simply use a piece of perf board in which you have soldered pins, since the pins are fortunately organized in a 1/10" array. Pin 13 is out of order, but it is not needed since pin 8 is also available for ground.

Figure 2.2-2 Monitor Connector

j

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2.3 The Centronics Interface

A standard Centronics parallel printer can be connected to this interface, provided that you have the proper cable. As you can see in Figure 2.3-2, the connection to the system is somewhat unusual. The data lines and the strobe of the universal port of the sound chip are used. So you find these too on the picture, in which the other lines, which will not be described in the section, will not disturb you. They belong to the disk drive and RS-232 interface and are handled there.

Here is the pin description:

I -STROBE indicates the validity of the byte on the data lines to the connected device by a low pulse.

2-9 DATA

II BUSY is always placed high by the printer when it is not able to receive additional data. This can have various causes. Usually the buffer is full or the device is off line.

18-25 GROUND.

All other pins are unused.

A tip for making a cable. Get flat-cable solderless connectors. You need a type D25-subminiature, a Cinch 36-pin (3M,AMP) and the appropriate length of 25-conductor flat ribbon cable. You squeeze the connectors on the cable so that pins 1 match up on both sides (they are connected together). The other connections then match automatically. Note that there will naturally be some pins free on the printer side.

Figure 2.3-1 Printer Port Pins

1 3

1

25

1 4

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2.4 The RS-232 Interface

This interface usually serves for communication with other computers and modems. You can also connect a printer here. Note the description of pin 5!

Figure 2.4-1 shows the connection to the system. Normally you don’t have to do any special programming to use this interface. It is taken care of by the operating system. Here the control of the interface is not controlled by a special IC (UART) as is usually the case, but the lines are serviced more or less "by hand." The shift register in the MFP is used for this purpose. The handshake lines however come from a wide variety of sources. Note this in the following pin description:

1 CHASSIS GROUND (shield)

This is seldom used.

2 TxD Send data

3 RxD Receive data

4 RTS

Ready to send comes from I/O port A bit 3 of the sound chip and is always high when the computer is ready to receive a byte. On the Atari, this signal is first placed low after receiving a byte and is kept low until the byte has been processed.

5 CTS

Clear to send of a connected device is read at interrupt input 12 of the MFP. At the present time this signal is handled improperly by the operating system. Therefore it is possible to connect only devices which "rattle" the line after every received byte (like the 520ST with RTS). The signal goes to input 12 of the MFP, but unfortunately is tested only for the signal edge. You will not have any luck connecting a printer because they usually hold the CTS signal high as long as the buffer is not full. There is no signal edge after each byte, which means that only the first byte of a text is transmitted, and then nothing.

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7 GND Signal ground.

8 DCD

Carrier signal detected. This line, which goes to interrupt input II of the MFP, is normally serviced by a modem, which tells the computer that connection has been made with the other party.

20 DTR

Device ready. This line signals to a device that the computer is turned on and the interface will be serviced as required. It comes from I/O port A bit 4 of the sound chip.

22 RI

Ring indicator is a rather important interrupt on 16 of the MFP and is used by a modem to tell the computer that another party wishes connection, that is, someone called.

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2.5 The MIDI Connections

The term MIDI is probably unknown to many of you. It is an abbreviation and stands for Musical Instrument Digital Interface, an interface for musical instruments.

It is certainly clear that we can't simply hook up a flute to this port. So first a little history. Music professionals (more precisely: keyboardists, musicians who play the synthesizer) demanded agreement between the various manufacturers to interface computers to musical instruments. They found it absurd to connect complicated set-ups with masses of wire. The idea was to service several synthesizers from one keyboard.

The tone created was basically analog (and still is, to a degree), so that the manufacturers agreed that a control voltage difference of IV corresponded to a difference in tone of 1 octave. This way one could play several devices under "remote control," but not service them.

This changed substantially when the change was made to digital tone creation. Here one didn't have to turn a bunch of knobs, there were buttons to press, whereby the basis for digital control was created.

Some manufacturers got together and designed a digital interface, the basic commands of which would be the same throughout, but which would still support the additional features of a given device.

The device is based on the teletype, the current-loop principle, which is not very susceptible to noise, but significantly faster. The transfer rate is 31250 baud (bits per second). The data format is set at one start bit, eight data bits, and one stop bit.

An IC can therefore be used for control which would otherwise be used for RS-232 purposes. You see the connection to the system in figure 2.5-1.

Logically, MIDI is multi-channel system, meaning that 16 devices can be serviced by one master, or a device with 16 voices. These devices are all connected to the same line (bus principle). To identify which device or which voice is intended, each data packet is preceded by the channel number. The device which recognizes this number as its own then executes the desired action.

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You may wonder what such an interface is doing in a computer. A computer can provide an entire arsenal of synthesizers with settings or complete melodies (sequencer) because of its high speed and memory capacity. It can also be used to record and store input from a synthesizer keyboard.

For this purpose the ST has the interfaces MIDI-IN and MIDI-OUT. The interfaces are even supported by the XBIOS so you don't have to worry about their actual operation.

The current loop travels on pins 4 and 5, out through pin 4 (+) of MIDI-OUT and in at 5, when a device is connected.

For MIDI-IN the situation is reversed because the current flows in through pin 4 and back out through pin 5. It goes though something called an optocoupler which electrically isolates the computer from the sender.

The received data are looped back to MIDI-OUT (pins 1 and 3), which implements the MIDI-THRU function, although not entirely according to the standard.

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2.6 The Cartridge Slot

The cartridge slot can be used exclusively for inserting ROM cartridges. Up to 128K in the address space $FA0000 to $FBFFFF can be addressed. The reason we stressed the exclusivity of the read access is the following. We thought it would be practical to outfit a cartridge with RAM and then load programs into it after the system start which would still remain after a reset. In order to try this we brought the R/-W signal to the outside. The experience taught us, however, that a write access to these addresses creates a bus error. The GLUE takes care of this. As you see, nothing is left to chance in the Atari.

Figure 2.6-1 The Cartridge Slot

1		=	+ 5VDC		2	1	=	Address	8
2		=	+ 5VDC		2	2	=	Address	14
3		=	Data 14		2	3	=	Address	7
4		=	Data 15		2	4	=	Address	9
5		=	Data 12		2	5	=	Address	6
6		=	Data 13		2	6	-	Address	10
7		=	Data 10		2	7	-	Address	5
8		=	Data 11		2	8	=	Address	12
9		—	Data 8		2	9	=	Address	11
1	0	=	Data 9		3	0	=	Address	4
1	1	=	Data 6		3	1	-	ROM Select	3
1	2	=	Data 7		3	2	=	Address	3
1	3	=	Data 4		3	3	=	ROM Select	4
1	4	=	Data 5		3	4	=	Address	2
1	5	=	Data 2		3	5	as	Dpper	Data	Strobe
1	6	=	Data 3		3	6	as	Address	1
1	7	=	Data 0		3	7	=	Lower	Data	Strobe
1	8	=	Data 1		3	8		G N D
1	9	=	Addre s s	13	3	9	=	GHD
2	0	=	Addre s s	15	4	0	=	G N D

Position :

1

2

3 9 40

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2.6.1 ROM Cartridges

We want to spend this section telling you how a program is put into ROM, as well as how the operating system recognizes and loads such a program.

These cartridges are technically feasible, since many manufacturers are now making ROM cartridge boards and programming devices for the ST computers.

The most important aspect is the first longword in ROM, which must contain an index number, or "magic number". This is read when the system start occurs — it checks to see whether there is a program cartridge or a diagnostic cartridge plugged into the cartridge port. The former must contain the index number $ABCDEF42, the latter the index number $FA52255F.

We wouldn't want to go any farther with the diagnostic cartridge. It should be enough that the operating system jumps to immediately test the address $FA0004 without initializing GEMDOS. You won't get any system processes anyway from this cartridge.

The program cartridges are what interest us. We can call up several programs from a ROM module of this type. Every program must have an introductory section, or application header, to be started by the operating system. The first must begin right after the magic number (from $FA0004), and must be made up of the following:

1 longword:

Address of the next header, when multiple programs reside in one cartridge. The header of the last (or only) program must contain $00000000.

1 longword:

Initialization code. This is where GEMDOS gets information, first about the handling of the program. In particular, this longword is made up of an address which points to the initialization routine (when needed). The most significant byte in this longword states at which point in time this routine should jump.

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This is arranged as follows:

BIT

0 The routine will be executed before the interrupt vectors, video RAM, etc., is installed.

1 The routine will be executed before GEMDOS is initialized.

3 The routine will be executed before GEMDOS is loaded. NOTE: This function is not accessible to computers which have GEMDOS in ROM!

5 Character which indicates that the program should be handled as an accessory.

6 Character which identifies the program as a .TOS type, and

not requiring the GEM system. _

7 Character which identifies the program as a .TTP type, and requiring starting parameters.

1 longword:

Starting address of the program, i.e. where it would start if you double-clicked it.

1 word:

Time in DOS format; has no meaning during runtime.

1 word:

Date in DOS format, see the previous entry.

1 longword:

Program length in bytes; has no meaning during runtime.

String:

Program name in explanatory text. The program name is inserted according to normal conventions, i.e., up to 8 characters, a period (.), and three characters after the period. NOTE: The string absolutely must be concluded by $00.

So, that's it. As for the rest: We've neglected to give you any information on clicking. Some program cartridges have their own icons, similar to a disk drive icon. Click this icon. It will show the programs contained in the cartridge; you may then start the desired program.

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2.7 The Floppy Disk Interface

The interface for floppy disk drives is conspicuous because of the unusual connector, a 14-pin DIN connector. All of the signals required for the operation of two disk drives are available on it.

You know most of the signals from the description of the disk controller 1772, since nine of the available connections are connected to the controller either directly or through a buffer. Only the drive select 1 and drive select 2 signals and the side 0 select are not derived from the disk controller. These signals come from port A of the sound chip.

Pinout of the disk connector:

1 READ DATA

2 SIDE 0 SELECT

3 GND

4 INDEX

5 DRIVE 0 SELECT

6 DRIVE 1 SELECT

7 GND

8 MOTOR ON

9 DIRECTION IN

10 STEP

11 WRITE DATA

12 WRITE GATE

13 TRACK 00

14 WRITE PROTECT

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2.8 The DMA Interface

This 19-pinjack can handle up to 8 DMA-compatible devices. These include hard disks, networks, and even coprocessors. The communications between the external devices and the ST run at a speed of up to 1 million bytes per second.

1-8

9

10

11

12

13

14

15

16

17

18

19

D0-D7

Bidirectional data lines CS

Chip Select, low-active. This line is activeated from the computer when either commands are sent to the device, or status bytes are read from there. If DMA transfer is in process, the signal is in a wait state. IRQ

Interrupt Request, low=active. This signal is produced by the device, and tells the computer that an action is done (e.g., DMA transfer).

GND

RST

Reset, low^active.

GND

ACK

Acknowledge, low-active. This signal only has meaning during DMA transfer. This indicates the device to the computer's DMA controller, depending on the data direction, whether a byte is received from the device or whether a legal data byte lies on the bus.

GND

A1

Address 1. This signal tells the device’s DMA controller whether the device address is set on bus with all commands (Al=low) or whether parameter bytes are handled (usually 5 parameter bytes; Al=high). GND R/W

Read/Write. This line also controls the controller, and is valid only when initializing. Write(=low): Command bytes snet; Read (=high): Waiting for a status byte.

DRQ

Data Request, low=active. This signal is produced from the device only during DMA transfer, depending upon data direction, when it can receive a byte from the controller; or otherwise, set a byte on the bus.

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There are two different methods of transfer. One is a computer controlled data transfer using the Al, CS and R/W lines. The other transfer of data, controlled from the device itself (the DMA transfer), runs without the computer with the help of the DRQ and ACK lines.

A connection can be seen between the chip description of the DMA controller, and the reset routine in the operating system, which checks for all eight possible DMA devices.

Figure 2.8-1 DMA Port

19 11

Figure 2.8-2 DMA Connections

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Chapter 3

\

The ST Operating System

3.1 The GEMDOS

3.1.1 Memory, files and processes

3.2 The BIOS Functions

3.3 The XBIOS

3.4 The Graphics

3.4.1 An overview of the line- A variables

3.4.2 Examples for using the line-A opcodes

3.5 The Exception Vectors

3.5.1 The line-F emulator

3.5.2 The interrupt structure of the ST

3.6 The ST VT52 Emulator

3.7 The ST System Variables

3.8 The 68000 Instruction Set

3.8.1 Addressing modes

3.8.2 The instructions

3.9 The BIOS listing

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The ST Operating System

GEMDOS-what is it? Is it in the ST? The operating system is supposed to be TOS, though. Or is it CP/M 68K? Or what?

These questions can be answered with few words. The operating system in the ST is named TOS— Tramiel Operating System-after the head of Atari. This TOS, in contrast to earlier information has nothing to do with CP/M 68K from Digital Research. At the start of development of the ST, CP/M 68K was implemented on it, but this was later changed because CP/M 68K is not exactly a model of speed and efficiency. A 68000 running at 8MHz and provided with DMA would be slowed considerably by the operating system.

At the beginning of 1985, Digital Research began developing a new operating system for 68000 computers, which would include a user-level interface. This operating system was named GEMDOS. It is exactly this GEMDOS which makes up the hardware-independent part of TOS. Like CP/M, TOS consists of a hardware-dependent and a hardware-independent part. The hardware-dependent part is the BIOS and the XBIOS, while the hardware-independent part is called GEMDOS. A large number of functions are built into GEMDOS, through which the programmer can control the actual input/output functions of the computer. Functions for keyboard input, text output on the screen or printer, and the operation of the various other interfaces are all present. Another quite important group contains the functions for file handling and for logical file and disk management.

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3.1 The GEMDOS

When you look at the functions available under GEMDOS, you will eventually come to the conclusion that the whole thing is not really new. All the functions in GEMDOS are very similar to the functions of the MS-DOS operating system. Even the functions numbers used correspond to those of MS-DOS. But not all MS-DOS functions are implemented in GEMDOS. Especially in the area of file management, only the UNIX compatible functions are implemented in GEMDOS. The "old" block-oriented functions which are included in MS-DOS to maintain compatibility with CP/M are missing from GEMDOS. Also, special functions relating to the hardware of MS-DOS computers (8088 processor) are missing.

Another essential difference between MS-DOS and GEMDOS is that for GEMDOS calls as well as for the BIOS and XBIOS, the function number, the number of the desired GEMDOS routine, and the required parameters are placed on the stack and are not passed in the registers. The 68000 is particularly suited to this type of parameters passing. GEMDOS is called with trap #1 and the function is executed according to the contents of the parameter list. After the call, the programmer must put the stack back in order himself, by clearing the parameters from memory.

The basic call of GEMDOS functions differs from the BIOS and XBIOS calls only in the trap number.

In regard to all GEMDOS calls, it must be noted that registers DO and AO are changed in all cases. If a value is returned, it is returned in DO, or DO may contain an error number, and after the call AO (usually) points to the stack address of the function number. Any parameters required in DO or AO must be placed there before GEMDOS is called.

The remainder of this section describes the individual GEMDOS functions.

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$00 TERM

C: void PtermO ()

Calling GEMDOS with function number 0 ends the running program and returns to the program from which it was started. For applications (programs started from the desktop), control is returned to the desktop. If the program was called from a different program, control is passed back to the calling program. This point is important for chaining program segments.

clr.w -(sp) trap

$01 CONIN

C: long CconinO

CONIN gets a single character from the keyboard. The routine waits until a character is available. The character read from the keyboard is returned in the DO register. The ASCII code of the pressed key is returned in the low byte of the low word, while the low byte of the high word of the register contains the scan code from the keyboard. This is important for reading keys which have no ASCII code, such as the 10 function keys or the editing keys. These keys return the ASCII value zero when pressed.

The scan code can be used to determine if the keypad or the main keys were pressed. These keys have identical ASCII codes, but different scan codes.

In addition, Shift status can be determined from the upper eight bits (bits 24 to 31) by calling Cconin. In this case, bits 24-31 correspond to bits 0 to 7 m BIOS function 1 1 ("kbshift"). The information can only be sent on a Cconin call when bit 3 of the memory location "conterm" (address $484) is set. If this bit is unset, then the shift bits after Cconin are deleted.

Cconin does not recognize <ControlxC>.

move.w #l,-(sp) trap #1 addq.l #2,sp

Function number on the stack Call GEMDOS Correct stack

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$02 CONOUT

C: void Cconout (c) int c ;

CONOUT also known as Cconout, represents the simplest and most primitive character output of GEMDOS. With this function only one character is printed on the screen. The character to be displayed is placed on the stack as the first word. The ASCII value of the character to be printed must be in the low byte of the word and the high byte should be zero:

The character printed by CONOUT is sent to device number 2, the normal normal! °Ut^Ut‘ ^'ontro^ characters and escape sequences are interpreted

move . w #65, -(sp) move . w #2, - (sp) trap #1 addq.l #4,sp

Output an A CONOUT Call GEMDOS Correct stack

$03 AUXILIARY INPUT

C : int Cauxin ( )

Tfie RS-232 interface of the ST goes under the designation "auxiliaiy port". A character can be read from the interface with the Cauxin function. The function returns when a character has been completely received. The character is returned in the lower eight bits of register DO.

move . w #3, - (sp) trap #1 addq.l #2,sp

Cauxin

Call GEMDOS, output character Correct stack Character in DO

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$04 AUXILIARY OUTPUT

C: void Cauxout (c) int c ;

A character can be transmitted over the serial interface, similar to the input of characters. With this function the programmer should clear the upper eight bits of the word and pass the character to be sent in the lower eight bits.

An A should be output Cauxout

Call GEMDOS, output character Correct stack

move.w #$41, -(sp) move.w #4,-(sp) trap #1 addq .1 # 4 , sp

$05 PRINTER OUTPUT

C: void Cprnout(c) int c;

PRINTER OUTPUT is the simplest method of operating a printer connected to the Centronics interface. One character is printed with each call.

An important part of PRINTER OUTPUT is the return value in DO. If the character was sent to the printer, the value - 1 ($FFFFFFFF) is returned m DO If after 30 seconds, the printer was unable to accept the character (not turned on, OFF LINE, no paper, etc.), GEMDOS returns a time out to the program. DO then contains a zero.

move . w move . w trap addq . 1 tst . w beq

#65, -(sp) #5, - (sp) #1

#4, sp DO

Output an A

Function number

Call GEMDOS, output character

Correct stack

Affect flags

printererror

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$06 RAWCONIO

C: long Crawio(c) int c ;

RAWCONIO is a somewhat unusual mixture of keyboard input and screen output; it also receives a parameter on the stack.

The keyboard is tested with a function value of $FF. If a character is present, the ASCII code and scan code are passed to DO as described for CONJN. If no key value is present, the value zero is passed as both the ASCII code and the scan code in DO. The call to RAWCONIO with parameter $FF is comparable to the BASIC INKEY$ function.

If a value other than $FF is passed to the function, the value is interpreted as a character to be printed and it is output at the current cursor position. This output also interprets the control characters and escape sequences properly.

START:
move . w	#$ff,-(sp)	Function value test keyboard
move . w	#6, - (sp)	Function number
trap	#1	Call GEMDOS, test keyboard
addq . 1	#4, sp	Correct stack
tst . w	DO	Character arrived?
beq	START	Not yet
cmp .b	#3, DO	AC selected as the end marker
beq	END
move	DO, - (sp)	Character for output on the stack
move	#6, - (sp)	Function number
trap	#1	Call GEMDOS, test keyboard
addq . 1	#4, sp	Correct stack
bra	START	Get new character

$07 DIRECT CONIN WITHOUT ECHO

C: long CrawcinO

The function $07 differs from $01 only in that the character received from the keyboard is not displayed on the screen. It waits for a key iust as does

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move . w	#8,- (sp)	Cauxin
trap	#1	Call GEMDOS,	output character
addq . 1	#2, sp	Adjust stack
■		Character in	DO

$08 CONIN WITHOUT ECHO

C: long CnecinO

Both function $08 and function $07 have exactly the same effect. The reason for this seemingly nonsensical behavior lies in the abovementioned compatibility to MS-DOS. Under MS-DOS these two functions are different in that with $08, certain keys not present on the ATARI are evaluated correctly, while this evaluation does not take place with function $07.

move . w #8,-(sp) Cauxin

trap #1 Call GEMDOS, output character

addq.l #2,sp Adjust stack

. Character in DO

$09 PRINT LINE

C: void Cconws(c) int c ;

You are already familiar with functions that output individual characters on the screen (see CONOUT and RAWCONIO). PRINT LINE offers you an easy way to output text. An entire string can be printed at the current cursor position with this function. To do this, the address of the string is placed on the stack as a parameter. The string itself is concluded with a zero byte. Escape sequences and control characters can also be displayed with this function.

After the call, DO contains the number of characters which were printed. The length of the string is not limited.

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move . 1	#text , - (sp)	Address of the string on the stack
move	#$09, - (sp)	Function number PRT LINE
trap	#1	Call GEMDOS
addq . 1	#6, sp	Clear the stack
text	.dc.b 'This	is the string to be printed' , $0D, $0A, 0

$0A READLINE

C; void Cconrs (buf ) char *buf ;

READLINE is a very easy-to-use function for reading characters from the keyboard. In contrast to the "simpler" character-oriented input functions, an entire input line can be taken from the keyboard with READLINE. The characters entered are displayed on the screen at the same time.

The address of an input buffer is passed to the function as the parameter. The value of the first byte of the input buffer determines the maximum length of the input line and must be initialized before the call. At the end of the routine, the second byte of the buffer contains the number of characters entered. The characters themselves start with the third byte.

The routine used by READLINE for keyboard input is quite different from the character-oriented console inputs. Escape sequences are not interpreted during the output. Only control characters like <ControlxH> (backspace) and <ControlxI> (TAB) are recognized and handled appropriately. The following control characters are possible:

AC	Ends input and program ( ! )
AH	Backspace one position
AI	TAB
AJ	Linefeed, end input
AM	CR, end input
AR	Entered line is printed in :	new	line
AU	Don't count line, start new	line
AX	Clear line, cursor at start	of	line

A function like AH (deleting a character entered) is useful, but for large programs you should write your own input routine because AC is very

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"dangerous." Unlike CP/M, the program will be ended even if the cursor is not at the very start of the input line.

If more characters are entered than were indicated in the first byte of the buffer at the initialization, the input is automatically terminated. If the input is terminated by ENTER, AJ, or AM, the terminating character will not be put in the buffer.

After the input, DO contains the number of characters entered, excluding ENTER, which can be found at buffer+1.

pea buffer move #$0A,-(sp) trap #1 addq. 1 #6, (sp)

buffer dc.b 20 dc .b 0 ds . b 20

Address of the input buffer Function number

Make room on stack

We want a maximum of 20 characters Number of given characters of the input buffer

$0B CONSTAT

C: int CConisO

All key presses are first stored in a buffer in the operating system. This buffer is 64 bytes in length. The key values stored there are taken from the buffer when a call to a GEMDOS output routine is made.

CONSTAT can be used to check if characters are stored in the keyboard buffer. After the call, DO contains the value zero or $FFFF. A zero in DO indicates that no characters are available.

testloop : move #$0B,-(sp) trap #1 addq. 1 #2, (sp) tst.w DO beq testloop

Function number

Make room on stack Character available? NO, then look again

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$0E SETDRV

C: long Dsetdrv(drv) int drv;

The current drive can be determined with the function SETDRV. A 16-bit parameter containing the drive specification is passed to the routine. Drive A is addressed with the number 0 and drive B with the number 1.

After the call, DO contains the number of the drive active before the call.

move #$2,-(sp) Drive C, e.g. RAMdisk

move #$0E,-(sp) Function number

trap #1

addq.l #4, (sp) Make room on stack

Previous current drive in DO

$10 CONOUT STAT

C: int CconosO

CONOUT STAT returns the console status in DO. If the value $FFFF is returned, a character can be displayed on the screen. If the returned value is zero, no character output is possible on the screen at that time. Incidentally, all attempts failed at creating a not-ready status at the console. The only imaginable possibility for the not-ready status would be if the output of the individual bit pattern of a character was interrupted and the interrupt routine itself tried to output a character. This case could not, however, be created.

move #$10, -(sp) Function number

trap #1

addq.l #2, (sp) Make room on stack

Always $FFFF in DO

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$11 PRTOUT STAT

C: int CprnosO

This function returns the status, the condition of the Centronics interface. If no printer is connected (or turned off, or off line), DO contains the value zero after the call to indicate "printer not available." If, however, the printer is ready to receive, DO contains the value $FFFF.

move #$11, -(sp) How's the printer doing? trap #1

addq.l #2, (sp) Make room on the stack

tst dO

beq printererror Go here if not ready

$12 AUXIN STAT

C: int Cauxis(c)

AUXIN STAT shows whether a character is available from the serial interface receiver ($FFFF) or not ($0000). The value is returned in DO.

waitloop :

move #$12, -(sp)

trap #1

addq. 1 #2, (sp)

tst dO

bne waitloop

We wait for a character from the serial interface Make room on the stack Is there a character there? No, not yet

$13 AUXOUT STAT

C: int Cauxos ()

AUXOUT STAT gives information about the state of the serial bus. A value of $FFFF indicates that the serial interface can send a character, while zero indicates that no characters can be sent at this time.

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waitloop:

move #$13, -(sp)

trap #1

addq. 1 #2, (sp)

tst dO

bne waitloop

Wait for a character from the serial interface Make room on the stack Received one yet?

No, not yet

$19 CURRENT DISK

C : int Dgetdrv ( )

For many applications it is necessary to know which drive is currently active. The current drive can be determined by the function $19. After the call, DO contains the number of the drive. The significance of the drive numbers is the same as for $0E, SET DRIVE (0=A, 1=B).

Which drive is active?

It will be sent over the serial interface Make room on the stack There will now be a character in DO between 'A' and 'P'

move #$19, -(sp) trap #1

addq.l #2, (sp)

ADD DO, 'A'

$1A SET DISK TRANSFER ADDRESS

C: void Fsetdta (buf ) char *buf ;

The disk transfer address is the address of a 44-byte buffer required for various disk operations (especially directory operations). Along with the GEMDOS functions SEARCH FIRST and SEARCH NEXT are examples for using the DTA.

move.l #DTADDRESS, - (sp) Address of the 44-byte DTA buffer

move.w #$la,-(sp) Function number SET DTA

trap #1 Set DTA

addq.l #6,sp Clean up the stack

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$20 SUPER

This function is especially interesting for programmers who want to access the peripherals or system variables available only in the supervisor mode while running a program in the user mode. After calling this function from user mode, the 68000 is placed in the supervisor mode. In contrast to the XBIOS routine for enabling the supervisor mode, additional GEMDOS, BIOS, and XBIOS calls can be made after a successful SUPER call.

Calling the SUPER function with a value of -1L ($FFFFFFFF) tells us the processor's current operating mode. If the result in DO after the call is 0, the processor is in user mode. A value of $0001 signifies that the processor is in supervisor mode. Switching modes is not carried out yet.

A program in user mode can call the SUPER function with a zero on the stack. In this case, the supervisor mode will be turned on. The supervisor stack pointer points to the current value of the user stack, and the original value of the supervisor stack is in DO. This value must be stored in the program to later return to the user mode. If the change to user mode is not made before the end of the program, the odds of a system crash are good.

If a value other than zero is passed to the SUPER function the first time it is called, this value is interpreted as the desired value of the supervisor stack pointer. In this case as well, DO contains the original value of the supervisor stack pointer, which the program should save.

As mentioned above, the user mode should be reenabled before the end of the program. This change of modes requires setting the address used by the supervisor stack pointer back to its original value.

The SUPER function differs from all other GEMDOS functions in one very important respect. Under certain circumstances, this call can also change the contents of A1 and Dl. If you store important values in these registers, you must save the values somewhere before calling the SUPER function.

clr . 1	- (sp)
move . w	#$20, -(sp)
trap	#1
add. 1	$6, sp
move . 1	dO , _S AVE_£

The 68000 is in the user mode User stack becomes supervisor stack Call SUPER

Supervisor mode is active after TRAP DO = old supervisor stack Save value

Here processing can be

done in the supervisor mode

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move.l _SAVE_SSP , - ( sp) Old supervisor stack pointer move . w #$20, -(sp) Call SUPER

trap #1 Now we are back in the user mode

add.l #6,sp

$2A GET DATE

C: int TgetdateO

You have no doubt experimented with the status field at one time or another. Among other functions, the status field contains a clock with time and date. It can be useful for some applications to have that data available. The date can be easily determined by GET DATE. This call requires no parameters and puts the date in the low word of register DO. It is thoroughly encoded, though, so the result in DO must be prepared to get the correct date.

The day in the range 1 to 3 1 is coded in the lower five bits. Bits 5 to 8 contain the month in the range 1 to 12, and the year is contained in bits 9 to 15. The range of these "year bits" goes from 0 to 1 19. The value of these bits must be added to the value 1980 to get the actual year. The date 12/12/1992, for example, would be %0001 100.1 100.01 100 in binary, or $198C in DO. The lengths of the three fields are marked with periods.

move	#$2a, - (sp)	We	want to get some data
trap	#1
addq . 1	#2, (sp)
move	dO , dl		Store	result in Dl for now
and	#%11111	, DO	Mask ■	the day bits and
move	dO , DAY		store	them
LSR	#5, dl		Shift	the 5 day bits
move	dl, dO
and	#%1111,	dO	and mask the month bits
move	DO, MONTH	Store	the month number
LSR	#4, dl		Shift	the month bits
move	dl, YEAR		Year .	is in Dl
DAY	ds . w	1
MONTH	ds . w	1
YEAR	ds . w	1

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$2B SET DATE

C: int Tsetdate (date) int date ;

The clock time and date can also be set from application programs. This is particularly interesting for programs which use the date and/or clock time. An example of this would be invoice processing in which the current date is inserted in the invoice. Such programs can then ask the user to enter the date. This avoids the problems that occur if the user forgets to set the date and clock time on the status field beforehand.

The date must be passed to the function SET DATE in the same format as it is received from GET DATE, bits 0-4 = day, bits 5-8 = month, bits 9-15 = year-1980.

move . w #%101101011001,-(sp) Set date to 10/25/1985

move.w #$2b,-(sp) Function number of SET DATE

trap #1 Set date

addq.l #4,sp Repair stack

$2C GET TIME

C: int TgettimeO

The function GET TIME returns the current (read: set) time from the GEMDOS clock. Similar to the date, the clock time is coded in a special pattern in individual bits of the register DO after the call. The seconds are represented in bits 0-4. But since only values from 0 to 31 can be represented in 5 bits, the internal clock runs in two second increments. In order to get the correct seconds-result the contents of these five bits must be multiplied by two. The number of minutes is contained in bits 5 to 10, while the remaining bits 11-15 give information about the hour in 24-hour format.

waitloop :

move #$2c,-(sp) trap #1 addq.l #2,sp move dO , dl

Is it noon yet?

Get the time from GEMDOS

Store result in Dl

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and	#$1111, DO	Store seconds in steps
move	DO, SEC	of two
LSR	#4, D1	Shift 4 second bits
bne	waitloop	No, not yet

$2D SET TIME

C: int Tsettime (time) int t ime ;

It is also possible to set the clock time under GEMDOS. The function SET TIME expects a 16- bit value (word) on the stack, in which the time is coded in the same form as that in which GET TIME returns the clock time.

When GEMDOS has the given time, DO returns the value 0; otherwise the value returned is $FFFFFFFF. GEMDOS handles time much as it does the date. Time changes through GEMDOS cannot be conveyed through the XBIOS. Select either XBIOS or GEMDOS. If you cross the two, you will end up with some very unpleasant complications.

move . w #%1000101010111101,-(sp) Clock time 17:21:58

move . w #$2D,-(sp) Function # of GET TIME

trap #1 Set date

addq.l #4,sp Repair stack

$2F GET DTA

C: long FgetdtaO

The function $2F is the counterpart of SET DTA ($1A). A call to GET DTA returns the current disk transfer buffer address in DO. A description of this buffer is found with the functions SEARCH FIRST and SEARCH NEXT.

move #$2f,-(sp) Function number Fgetdta

trap #1 Get DTA

addq.l #2fsp

move.l dO , DTAPOINTER and mark for later

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$30 GET VERSION NUMBER

C: int SversionO

Calling this function returns in DO the version number of GEMDOS. In the version of GEMDOS currently in release, this question is always answered with $0D00, corresponding to version 13.00. Official Atari documentation claims that a value of $0100 should be returned for this version, though perhaps the value should indicate that the present GEMDOS version is the $D = diskette version.

move #30, -(sp) trap #1 addq.l #2,sp cmp #$1300, dO

bne not tos

Look to see which version we have

The recognized version? It can't be given

$31 KEEP PROCESS

C: void Ptermres (keepcnt, retcode) long keepcnt; int retcode;

This function is comparable to the GEMDOS function TERM $00. The program is also ended after a call to this function. $3 1 does differ from $00 in several important points.

After processing TRAP#1, like TERM, control is passed back to the program which started the program just ended. In contrast to TERM, a termination condition can be communicated to the caller. While TERM returns the termination value zero (no error), zero or one may be selected as the termination value for $31. A value other than zero means that an error occurred during program processing.

Another essential point lies in the memory management of GEMDOS. When a program is started, the entire available memory space is made available to it. If the program is ended with TERM, the memory space is released and made available to GEMDOS. The entire area of memory released is also cleared, filled with zeros. The program actually physically disappears from the memory. With function $31, however, an area of memory can be

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protected at the start address of the program. This memory area is not released when the program is ended and it is also not cleared. The program could be restarted without having to load it in again.

Practical applications for Ptermres() are spoolers, RAM disks and other utilities which are installed once and remain in memory for storage or processing. At the same time, such programs must be ended correctly after installation to allow other programs to be loaded and started.

KEEP PROCESS is called with two parameters. The example program shows the parameter passing. It is also important that memory additionally reserved for programs be Malloc not be freed up. If files are opened by PtermresQ at that time, these will be closed by GEMDOS.

move . w #0, - (sp) move . 1 #$1000, -(sp) move . w #$31, -(sp) trap #1

Error code no error, else 1 Protect $1000 bytes at program start Function number, end program . . . .now.

This time, don’t clear the stack!

$36 GET DISK FREE SPACE

C: void Dfree (buffer, drive) long *buffer int drive

It can be very important for disk-oriented programs to determine the amount of free space on the diskette, then warn the user to change disks. "Disk full" messages or even data loss can then be avoided.

Function $36, Dfree(), returns this information. The number of the desired disk drive and the address of a 16-byte buffer must be passed to the function. If the value 0 is passed as the drive number, the information is fetched from the active drive, a 1 takes the information from drive A, and a 2 from drive B.

The information passed in the buffer is divided into four long words. The first longword contains the number of free allocation units. Each file, even if it is only eight bytes long, requires at least one such allocation unit.

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The second longword gives information about the number of allocation units present on the disk, regardless of whether they are already used or are still free. For the "small" single-sided diskettes this value is $15C or 351, while the double-sided disks have $2C7 = 711 allocation units.

The third longword contains the size of a disk sector in bytes. For the Atari this is always 512 bytes ($200 bytes).

The last longword is the number of physical sectors belonging to an allocation unit. This is normally 2. Two sectors form one allocation unit.

The amount of free disk space can be easily calculated from this data.

move . w	#0, - (sp)	Information from the active drive
pea	BUFFER	Address of the 16-byte buffer
move	#$36, -(sp)	Function number
trap	#1
addq. 1	#6, sp	Clean up stack

BUFFER: f real :	-ds . 1	1	Free allocation units
total :	• ds . 1	1	Total allocation units
bps :	• ds . 1	1	Bytes/physical sector
pspal :	. ds.l	1	Phys. sectors/alloc, u

$39 MKDIR

C: int Dcreate (path) char *path;

A subdirectory can be created from the desktop with the menu option "NEW FOLDER". Such a subdirectory can also be created from an application program with a call to $39.

In order to create a new folder, the function $39 is given the address of the folder name, also called the pathname. This name may consist of 8 characters and a three-character extension. The same limitations apply to pathnames as do to filenames. The pathname must be terminated with a zero byte when calling MKDIR.

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After the call, DO indicates whether the operation was performed successfully. If DO contains a zero, the call was successful. Errors are indicated through a negative number in DO. At the end of this chapter you will find an overview of all of the error messages occurring in connection with GEMDOS functions.

move . 1 pathname move #$39, -(sp) trap #1 addq.l #6,sp tst.w dO bne error

pathname :

.dc.b 'private .dat 0

$3 A RMDIR

C: int Ddelete (path) char *path;

A subdirectory created with MKDIR can be removed with $3A. As before, the pathname, terminated with a zero, is passed to RMDIR. The error messages also correspond to those for MKDIR, with zero for success or a negative value for errors. An important error message should be mentioned at this point. It is the message -36 ($FFFFFFCA). This is the error message you get when the subdirectory you are trying to remove contains files.

Only empty subdirectories can be removed with RMDIR. If you get an error, erase directory files with UNLINK ($41), then call RMDIR again.

Address of the pathname Function number

Repair stack Error occurred? Apparently

pea pathname move.w #$3A,-(sp) trap #1 addq.l #6,sp tst.w DO bne era sub dir

Address of the pathname Function #

Repair stack

Is there an error?

It appears that way

pathname :

.dc.b ' tmpfiles .a_z ' , 0

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$3B CHDIR

C: int Dsetpath (path) char *path;

The system of subdirectories available under GEMDOS is exactly the same form available under UNIX. This system is now running on systems with diskette drives, but its advantages become noticeable first when a large mass storage device such as a hard disk with several megabytes of storage capacity is connected to the system. After a while, most of the time would probably be spent looking for files in the directory.

To better organize the data, subdirectories can be placed within subdirectories. It can therefore become necessary to specify several subdirectories until one has the directory in which the desired file is stored. An example might be:

\hugos . dat \cf iles . s\csorts . s\cqsort . s

Translated this would mean: load the file cqsort . s from the subdirectory csorts . s. This subdirectory c sorts . s is found in the subdirectory cf iles . s, which in turn is a subdirectory of hugos . dat. If the whole expression is given as a filename, the desired file will actually be loaded (assuming that the file and all of the subdirectories are present). If you want to access another file via the same path (do you understand the term pathname?), the entire path must be entered again. But you can also make the subdirectory specified in the path into the current directory, by calling CHDIR with the specification of the desired path. After this, all of the files in the selected subdirectory can be accessed just by the filenames. The path is set by the function.

move.l path,-(sp) raove.w #$3b,-(sp) trap #1 addq.l #6,sp tst.w dO bne error

Address of the path Function number

Repair stack Error occurred? Apparently

path :

.dc.b ' \hugos .dat\cf iles . s\csorts . s\cqsort . s ' , 0

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$3C CREATE

C: int Fcreate (fname, attr) char *fname; int attr;

In all operating systems, the files are accessed through the sequence of opening the file, accessing the data (reading or writing), and then closing the file. This "trinity" also exists under GEMDOS, although there is an exception. Under CP/M, for example, a non-existent file can also be opened. When a file which does not exist is opened, it is created. Under GEMDOS, the file must first be created. The call $3C, CREATE, is used for this purpose. Two parameters are passed to this GEMDOS function: the address of the desired filename, and an attribute word.

If a zero is passed as the attribute word, a normal file is created, a file which can be written to as well as read from. If the value 1 is passed as the attribute the file will only be able to be read after it is closed. This is a type of software write-protect (which naturally cannot prevent the file from disappearing if the disk is formatted).

Other possible attributes are $02, $04, and $08. Attribute $02 creates a "hidden" file and attribute $04 a "hidden" system file. Attribute $08 creates a file with a "volume label." The volume label is the (optional) name which a disk can be given when it is formatted. The disk name is then created from the maximum of 1 1 characters in the name and the extension. Files with one of the last three attributes are excluded from the normal directory search in the Desktop. On the ST, however, they appear in the directory, e.g. as COMMAND.PRG.

When the function CREATE is ended, a file descriptor, also called a file handle, is returned in DO. All additional accesses to the file take place over this file handle (a numerical value between 6 and 45). The handle must be given when reading, writing, or closing files. A total of $28 = 40 files can be opened at the same time.

If CREATE is called and a file with this name already exists, it is cut off at zero length. This is equivalent to the sequence delete the old file and create a new file with the same name, but it goes much faster.

If after calling CREATE you get a handle number back in DO, the file need not be opened again with $3D OPEN.

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move . w	#$o,-	(sp)	File should have R/W status
pea	filename	Address of the filename on	stack
move . w	#$3c, ■	- (sp)	Fcreate function number
trap	#1		Call GEMDOS
addq . 1	#8 , sp		Clean up stack
tst	dO		Error occurred?
bmi	error		It appears so
move	dO, handle	Save file handle for later	access
filename :		Don't forget the zero	byte
	.dc .b	'myf ile	i .dat ' , 0
handle	:
	. ds . w	1

$3D OPEN

C: int Fopen (f name, mode) char *fname; int mode;

You can only create new files with CREATE, or shorten existing files to zero length. But you must be able to process existing files further as well. To do this, such files must be opened with the OPEN function.

The first parameter of the OPEN function is the mode word. With a zero in the mode word, the opened file can only be read, with one it can only be written. With a value of 2, the file can be read as well as written. The filename, ended with a zero byte, is passed as the second parameter.

The OPEN function returns the handle number in DO as the result if the file is present and the desired access mode is possible. Otherwise DO contains an error number. See the end of the chapter for a list of the error numbers.

Up until now, when we've discussed file functions, we have referred only to files. This is only half the story; devices can be opened and closed as well as files. These devices are the console (keyboard) and monitor, the serial port and the printer connection. See Chapter 3.1.1 for more information on GEMDOS and the file/device concept. We want to show you for now how a device is opened, and what handle to give it. This information is important insofar as device handles are different from file handles.

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To open a device, the device name is given as a filename. The device names are: "CON:" for the console, "AUX:" for the serial interface and "PRN:" for the printer interface. After opening with the appropriate name, you'll get a word-negative handle. $FFFF(-1) is returned for CON:, $FFFE(-2) is returned for AUX: and $FFFD(-3) is the handle for the printer port.

move . w	#$2 , - ( sp)	File read and write
pea filename	Address of the filename on the stack
move . w	#$3d, - (sp)	Function number
trap	#1	Call GEMDOS
addq. 1	#8, sp	Clean up the stack
tst . 1	dO	Error occurred?
bmi	error	Apparently
move	dO , f handle	Save file handle for later accesses
filename: Don't forget zero byte! .dc.b 'myf ile . dat 1 , 0 handle : .ds.w 1

$3E CLOSE

C: int Fclose (handle) int handle;

Every opened file should be closed when it is no longer needed within a program, or when the program itself is ended. Especially when writing, files must absolutely be closed before the program ends or data may be lost.

Files are closed by the call CLOSE, to which the handle number is passed as a parameter. The return value will be zero if the file was closed correctly.

Handle number Function number Call GEMDOS Error occurred? Apparently

handle :

.ds.w 1

move.w handle, -(sp) move.w #$3e,-(sp) trap #1 addq.l #4,sp bmi error

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$3F READ

C: long Fread (handle, count, buff) int handle; long count; char *buf f ;

Opening and closing files is naturally only half of the matter. Data must be stored and the retrieved later. Reading such files can be done in a very elegant manner with the function READ. READ expects three parameters: first the address of a buffer in which the data is to be read, then the number of bytes to be read from the file, and finally the handle number of the file. This number you have (hopefully) saved from the previous OPEN.

As return value, DO contains either an error number (hopefully not) or the number of bytes read without error. No message regarding the end of the file is returned. This is not necessary, however, since the size of the file is contained in the directory entiy (see SEARCH FIRST/SEARCH NEXT). If the file is read past the logical end, no message is given. The reading will be interrupted at the end of the last occupied allocation unit of the file. The number of bytes read in this case is always divisible by $400.

pea	buffer	Address of the data buffer
move . 1	#$100, -(sp)	Read 256 bytes
move . w	handle, - (sp)	Space for the handle number
move . w	#$3f , - (sp)	Function number
trap	#1
add. 1	#12, sp
tst . 1	dO	Did an error occur
bmi	error	Apparently
cmp . 1	#$100, dO	256 bytes read?
bne	end_of_f ile	Not enough data in file
handle :
	.ds.w 1	Space for the handle number
buffer :
	•ds.b $100	Suffices in our example

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$40 WRITE

C: long Fwrite (handle, count, buff) int handle; long count; char *buff;

Writing to a file is just as simple as reading from it. The parameters required are also the same as those required for reading. The file descriptors from OPEN and CREATE calls can be used as the handle, but the device numbers listed for READ can also be used. The output of a program can be sent to the screen, the printer, or in a file just by changing the handle number.

pea	buffer		Address of the data buffer
move . 1	#$100,-	- (sp)	Read 256 bytes
move . w	handle	(sp)	Space for the handle	number
move . w	#$40,-	(sp)	WRITE request
trap	#1
add. 1	#12, sp
tst . 1	dO		Did an error occur?
bmi	error		Apparently
handle
	. ds . w	1	Space for the handle	number
buffer	;
	. ds .b	$100	Suffices in our example

$41 UNLINK

C: int Fdelete (fname) char * fname;

Files which are no longer needed can be deleted with UNLINK. To do this, the address of the filename or, if necessary, the complete pathname must be passed to the function. If the DO register contains a zero after the call, the file has been deleted. Otherwise DO will contain an error number.

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pea fname

move.w #$41, -(sp) trap #1 add.l #6,sp tst.l dO bmi error

fname :

. dc . b 'b : \hugos . dat\cf iles\csorts\cqsort . s ' , 0

Name of the file to be scratched Function number FdeleteO

Did an error occur? Apparently

$42 LSEEK

C: long Fseek (of f set, handle, seekmode) long offset; int handle; int seekmode;

Up to now we have become acquainted only with sequential data accesses. We can read through any file from the beginning until we come the desired information. An internal file pointer which points to the next byte to be read goes along with each read. We can only move this pointer continuously in the direction of the end of file by reading. A few bytes forward or backward, setting the pointer as desired, is not something we can do. This is required for many applications, however.

LSEEK offers an extraordinarily easy-to-use method of setting the file pointer to any desired byte within the file and to read or write at this point.This UNIX-compatible option of GEMDOS is much easier to use than the relative file management methods available under CP/M, for instance.

A total of three parameters are passed to the LSEEK function. The first parameter specifies the number of bytes by which the pointer should be moved. An additional parameter is the handle number of the file. The last parameter is a mode word which describes how the file is to be moved. A zero as the mode moves the pointer to the start of the file and from there the given number of bytes toward the end of the file. Only positive values may be used as the number. With a mode value of 1, the pointer is moved the desired positive or negative amount from the current position, and a 2 as the mode value means the distance specified is from the end of the file. Only negative values are allowed in this mode.

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After the call, DO contains the absolute position of the pointer from the